C++ (Cpp) sh_eth_ring_format Examples

Example #1

File: sh_eth.c Project: artm1248/linux

static int sh_eth_dev_init(struct net_device *ndev)
{
    int ret = 0;
    struct sh_eth_private *mdp = netdev_priv(ndev);
    u32 ioaddr = ndev->base_addr;
    u_int32_t rx_int_var, tx_int_var;
    u32 val;

    /* Soft Reset */
    sh_eth_reset(ndev);

    /* Descriptor format */
    sh_eth_ring_format(ndev);
    ctrl_outl(RPADIR_INIT, ioaddr + RPADIR);

    /* all sh_eth int mask */
    ctrl_outl(0, ioaddr + EESIPR);

#if defined(CONFIG_CPU_SUBTYPE_SH7763)
    ctrl_outl(EDMR_EL, ioaddr + EDMR);
#else
    ctrl_outl(0, ioaddr + EDMR);	/* Endian change */
#endif

    /* FIFO size set */
    ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR);
    ctrl_outl(0, ioaddr + TFTR);

    /* Frame recv control */
    ctrl_outl(0, ioaddr + RMCR);

    rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
    tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
    ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);

#if defined(CONFIG_CPU_SUBTYPE_SH7763)
    /* Burst sycle set */
    ctrl_outl(0x800, ioaddr + BCULR);
#endif

    ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR);

#if !defined(CONFIG_CPU_SUBTYPE_SH7763)
    ctrl_outl(0, ioaddr + TRIMD);
#endif

    /* Recv frame limit set register */
    ctrl_outl(RFLR_VALUE, ioaddr + RFLR);

    ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
    ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR);

    /* PAUSE Prohibition */
    val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
          ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

    ctrl_outl(val, ioaddr + ECMR);

    /* E-MAC Status Register clear */
    ctrl_outl(ECSR_INIT, ioaddr + ECSR);

    /* E-MAC Interrupt Enable register */
    ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR);

    /* Set MAC address */
    update_mac_address(ndev);

    /* mask reset */
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763)
    ctrl_outl(APR_AP, ioaddr + APR);
    ctrl_outl(MPR_MP, ioaddr + MPR);
    ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
    ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR);
#endif

    /* Setting the Rx mode will start the Rx process. */
    ctrl_outl(EDRRR_R, ioaddr + EDRRR);

    netif_start_queue(ndev);

    return ret;
}

Example #2

File: sh_eth.c Project: andi34/Dhollmen_Kernel

static int sh_eth_dev_init(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u_int32_t rx_int_var, tx_int_var;
	u32 val;

	/* Soft Reset */
	sh_eth_reset(ndev);

	/* Descriptor format */
	sh_eth_ring_format(ndev);
	if (mdp->cd->rpadir)
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);

	/* all sh_eth int mask */
	sh_eth_write(ndev, 0, EESIPR);

#if defined(__LITTLE_ENDIAN__)
	if (mdp->cd->hw_swap)
		sh_eth_write(ndev, EDMR_EL, EDMR);
	else
#endif
		sh_eth_write(ndev, 0, EDMR);

	/* FIFO size set */
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);

	/* Frame recv control */
	sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);

	rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
	tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
	sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);

	if (mdp->cd->bculr)
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */

	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);

	if (!mdp->cd->no_trimd)
		sh_eth_write(ndev, 0, TRIMD);

	/* Recv frame limit set register */
	sh_eth_write(ndev, RFLR_VALUE, RFLR);

	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);

	/* PAUSE Prohibition */
	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
		ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

	sh_eth_write(ndev, val, ECMR);

	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

	/* E-MAC Status Register clear */
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);

	/* E-MAC Interrupt Enable register */
	sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
	if (mdp->cd->apr)
		sh_eth_write(ndev, APR_AP, APR);
	if (mdp->cd->mpr)
		sh_eth_write(ndev, MPR_MP, MPR);
	if (mdp->cd->tpauser)
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);

	/* Setting the Rx mode will start the Rx process. */
	sh_eth_write(ndev, EDRRR_R, EDRRR);

	netif_start_queue(ndev);

	return ret;
}