static void sh_wdt_start(struct sh_wdt *wdt) { unsigned long flags; u8 csr; spin_lock_irqsave(&shwdt_lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); mod_timer(&wdt->timer, next_ping_period(clock_division_ratio)); csr = sh_wdt_read_csr(); csr |= WTCSR_WT | clock_division_ratio; sh_wdt_write_csr(csr); sh_wdt_write_cnt(0); csr = sh_wdt_read_csr(); csr |= WTCSR_TME; csr &= ~WTCSR_RSTS; sh_wdt_write_csr(csr); #ifdef CONFIG_CPU_SH2 csr = sh_wdt_read_rstcsr(); csr &= ~RSTCSR_RSTS; sh_wdt_write_rstcsr(csr); #endif spin_unlock_irqrestore(&shwdt_lock, flags); }
static int sh_wdt_start(struct watchdog_device *wdt_dev) { struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev); unsigned long flags; u8 csr; pm_runtime_get_sync(wdt->dev); clk_enable(wdt->clk); spin_lock_irqsave(&wdt->lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); mod_timer(&wdt->timer, next_ping_period(clock_division_ratio)); csr = sh_wdt_read_csr(); csr |= WTCSR_WT | clock_division_ratio; sh_wdt_write_csr(csr); sh_wdt_write_cnt(0); /* * These processors have a bit of an inconsistent initialization * process.. starting with SH-3, RSTS was moved to WTCSR, and the * RSTCSR register was removed. * * On the SH-2 however, in addition with bits being in different * locations, we must deal with RSTCSR outright.. */ csr = sh_wdt_read_csr(); csr |= WTCSR_TME; csr &= ~WTCSR_RSTS; sh_wdt_write_csr(csr); #ifdef CONFIG_CPU_SH2 csr = sh_wdt_read_rstcsr(); csr &= ~RSTCSR_RSTS; sh_wdt_write_rstcsr(csr); #endif spin_unlock_irqrestore(&wdt->lock, flags); return 0; }
/** * sh_wdt_start - Start the Watchdog * * Starts the watchdog. */ static void sh_wdt_start(void) { __u8 csr; next_heartbeat = jiffies + (heartbeat * HZ); mod_timer(&timer, next_ping_period(clock_division_ratio)); csr = sh_wdt_read_csr(); csr |= WTCSR_WT | clock_division_ratio; sh_wdt_write_csr(csr); sh_wdt_write_cnt(0); /* * These processors have a bit of an inconsistent initialization * process.. starting with SH-3, RSTS was moved to WTCSR, and the * RSTCSR register was removed. * * On the SH-2 however, in addition with bits being in different * locations, we must deal with RSTCSR outright.. */ csr = sh_wdt_read_csr(); csr |= WTCSR_TME; csr &= ~WTCSR_RSTS; sh_wdt_write_csr(csr); #ifdef CONFIG_CPU_SH2 /* * Whoever came up with the RSTCSR semantics must've been smoking * some of the good stuff, since in addition to the WTCSR/WTCNT write * brain-damage, it's managed to f**k things up one step further.. * * If we need to clear the WOVF bit, the upper byte has to be 0xa5.. * but if we want to touch RSTE or RSTS, the upper byte has to be * 0x5a.. */ csr = sh_wdt_read_rstcsr(); csr &= ~RSTCSR_RSTS; sh_wdt_write_rstcsr(csr); #endif }