t_stat tti_svc (UNIT *uptr) { int32 c; sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((dev_done & INT_TTI) && /* prior character still pending and < 500ms? */ ((sim_os_msec () - tti_buftime) < 500)) return SCPE_OK; if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) /* break? */ uptr->buf = 0; else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags) | TTUF_KSR); tti_buftime = sim_os_msec (); uptr->pos = uptr->pos + 1; dev_done = dev_done | INT_TTI; /* set done */ int_req = INT_UPDATE; /* update interrupts */ return SCPE_OK; }
t_stat tti_svc (UNIT *uptr) { int32 c; sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */ if ((tti_csr & CSR_DONE) && /* input still pending and < 500ms? */ ((sim_os_msec () - tti_buftime) < 500)) return SCPE_OK; if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) /* break? */ tti_buf = RXDB_ERR | RXDB_FRM; else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); tti_buftime = sim_os_msec (); uptr->pos = uptr->pos + 1; tti_csr = tti_csr | CSR_DONE; if (tti_csr & CSR_IE) tti_int = 1; return SCPE_OK; }
t_stat tti_svc (UNIT *uptr) { int32 c; sim_clock_coschedule_tmr (uptr, TMR_CLK, TMXR_MULT); /* continue poll */ if ((tti_csr & CSR_DONE) && /* input still pending and < 500ms? */ ((sim_os_msec () - tti_buftime) < 500)) return SCPE_OK; if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ return c; if (c & SCPE_BREAK) { /* break? */ if (sysd_hlt_enb ()) /* if enabled, halt */ hlt_pin = 1; tti_unit.buf = TTIBUF_ERR | TTIBUF_FRM | TTIBUF_RBR; } else tti_unit.buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); tti_buftime = sim_os_msec (); uptr->pos = uptr->pos + 1; tti_csr = tti_csr | CSR_DONE; if (tti_csr & CSR_IE) SET_INT (TTI); return SCPE_OK; }