int mmc_wait_card_ready(SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
int retry=0;
ext = (SIM_MMC_EXT *)hba->ext;
if(!(ext->hccap & MMC_HCCAP_NOCD_BUSY)){
return (MMC_SUCCESS);
}
while(retry++ <ext->busy_retry){
if(mmc_get_card_status(hba)!=MMC_SUCCESS){
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: failed %x", __func__, ext->mmc_resp[0]);
break;
}
if( ext->mmc_resp[0] & 0x100){
return MMC_SUCCESS;
}
//TOD. what about error status (not in programming state)
}
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: timeout, card status %x", __func__, ext->mmc_resp[0]);
return MMC_FAILURE;
}
void
omap_clock_enable(DEV_OMAP* dev, clk_enable_t clk_cfg)
{
int enable_rc = 0;
int functional_rc = 0;
/* Our idle state can be changed by the ISR so we must use a spinlock */
InterruptLock(&dev->idle_spinlock);
/* Only enable clocks if they aren't enabled already */
if (dev->idle == 0) {
goto done;
}
if (dev->clkctrl_base) {
/* Enable the clock */
out32(dev->clkctrl_base, OMAP_CLKCTRL_MODMODE_ENABLE);
/* Wait for the module mode to have been written */
enable_rc = poll_for_condition(dev->clkctrl_base, OMAP_CLKCTRL_MODMODE_MASK, OMAP_CLKCTRL_MODMODE_ENABLE);
/* Wait for the module idle status to report "fully functional" */
functional_rc = poll_for_condition(dev->clkctrl_base, OMAP_CLKCTRL_IDLEST_MASK, OMAP_CLKCTRL_IDLEST_FUNCTIONAL);
/* Re-configure clock if specified otherwise simply skip it */
if (clk_cfg != clk_enable_skip) {
/* Set the idle mode to smart idle with wake up */
set_port(dev->port[OMAP_UART_SYSC], OMAP_UART_SYSC_IDLEMODE_MASK, clk_cfg);
}
/* Enable the CTS wakeup */
write_omap(dev->port[OMAP_UART_WER], OMAP_UART_WER_CTS_ENABLE);
/* Indicate clocks are enabled */
dev->idle = 0;
}
done:
#ifdef WINBT
/* clear CTS debounce timer and OHW_PAGED flag */
if (dev->tty.un.s.spare_tmr > 0) {
dev->tty.un.s.spare_tmr = 0;
if (dev->tty.flags & OHW_PAGED)
atomic_clr (&dev->tty.flags, OHW_PAGED);
}
#endif
omap_uart_ctx_restore(dev);
InterruptUnlock(&dev->idle_spinlock);
/* Don't slog while interrupts are disabled - otherwise slogf() will re-enable interrupts */
if (enable_rc) {
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: Failed to set module mode to 'enabled'", __FUNCTION__);
}
if (functional_rc) {
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: Module failed to report 'fully functional'", __FUNCTION__);
}
}
static int hsmci_args (SIM_HBA *hba, char *options)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
char *value;
int opt;
int val;
int idx;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
for (idx = 0; idx < strlen(options); idx++) {
if (':'==options[idx])
options[idx] = ',';
}
strlwr(options);
if (*options == '\0')
return (0);
while (*options != '\0') {
if ((opt = getsubopt(&options, opts, &value)) == -1)
continue;
switch (opt) {
case 0:
val = strtoull(value, 0, 0);
if ((val > 1) || (val < 0)) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR,
"MMC: wrong MCI port option %d", val);
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR,
"MMC: G45 MCI port must be 0 or 1");
}
else {
hsmci->port = val;
}
break;
default:
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR,
"MMC: Unrecognized options %s\n", value);
return (-1);
}
}
return (0);
}
static int twl4030_i2c_read(int fd, uint8_t addr, uint8_t reg, uint8_t * val)
{
struct send_recv
{
i2c_sendrecv_t hdr;
uint8_t buf[2];
} twl4030_rd_data;
/*Read the Registers Current Value */
twl4030_rd_data.buf[0] = reg;
twl4030_rd_data.hdr.send_len = 1;
twl4030_rd_data.hdr.recv_len = 1;
twl4030_rd_data.hdr.slave.addr = addr;
twl4030_rd_data.hdr.slave.fmt = I2C_ADDRFMT_7BIT;
twl4030_rd_data.hdr.stop = 1;
if (devctl(fd, DCMD_I2C_SENDRECV, &twl4030_rd_data, sizeof(twl4030_rd_data), NULL))
{
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "BEAGLE MMCSD: twl4030_i2c_read fail");
return -1;
}
*val = twl4030_rd_data.buf[0];
return 0;
}
/*
* The real PIO transfer.
* Note:
* We only use PIO to read SCR and check/switch high speed mode, so only read operation is possible
*/
static int _hsmci_pio_done(SIM_HBA *hba, char *buf, int len, int dir)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
int i;
int timeout = TIMEOUT_LOOPS;
uint32_t *buf32 = (uint32_t *) buf;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
// Make sure the data is ready
while (!(READ32(MCI_SR) & RXRDY) && timeout--);
if (dir == DATA_READ) {
for (i = 0; i < len; i+=4) {
*buf32++ = READ32(MCI_RDR);
delay(5);
}
} else {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: We only support PIO read\n", __func__);
return -1;
}
clearFIFO (hba);
return len;
}
static int _hsmci_wait_stat (SIM_HBA *hba, mmc_cmd_t *cmd)
{
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
uint32_t mask = CMDRDY;
ext = (SIM_MMC_EXT *)hba->ext;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
if (cmd->eflags & MMC_CMD_DATA) {
mask |= NOTBUSY | XFRDONE;
}
int timeout = TIMEOUT_LOOPS/100;
while (((READ32(MCI_SR) & mask) != mask) && timeout--)
nanospin_ns(100);
if (timeout <= 0) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: timeout on waiting for MCI_SR: 0x%x for CMD%d, mask: 0x%x", READ32(MCI_SR), cmd->opcode, mask);
return MMC_FAILURE;
}
return MMC_SUCCESS;
}
void setVolume(int level)
{
int volume;
snd_mixer_t *mixer_handle;
if (snd_mixer_open (&mixer_handle, card, device) < 0) {
slogf( _SLOG_SETCODE(_SLOGC_AUDIO, 0), _SLOG_CRITICAL, "Unable to open mixer\n");
return;
}
snd_mixer_group_read(mixer_handle, &group);
volume = (float)(group.max - group.min) * ( level / 100.0) + group.min;
if (group.channels & SND_MIXER_CHN_MASK_FRONT_LEFT)
group.volume.names.front_left = volume;
if (group.channels & SND_MIXER_CHN_MASK_REAR_LEFT)
group.volume.names.rear_left = volume;
if (group.channels & SND_MIXER_CHN_MASK_FRONT_CENTER)
group.volume.names.front_center = volume;
if (group.channels & SND_MIXER_CHN_MASK_FRONT_RIGHT)
group.volume.names.front_right = volume;
if (group.channels & SND_MIXER_CHN_MASK_REAR_RIGHT)
group.volume.names.rear_right = volume;
if (group.channels & SND_MIXER_CHN_MASK_WOOFER)
group.volume.names.woofer = volume;
snd_mixer_group_write(mixer_handle, &group);
snd_mixer_close (mixer_handle);
}
static int dmac_setup_xfer (dmac_dev_t * dmac_dev, paddr_t paddr, int len, int dir)
{
int i, blknum = len/dmac_dev->blksz;
dmac_dev->blknum = blknum;
memset(dmac_dev->lli, 0, blknum * sizeof(at91sam9xx_dmac_bd_t));
/* Resume Channel */
dmac_dev->dmac->chdr = 1 << (dmac_dev->chid + 8);
if (dir == DATA_READ) { /* Block READ */
/* Setup DMA direction */
dmac_dev->dmac->lli[dmac_dev->chid].cfg &= ~(DMAC_DST_H2SEL_SW | DMAC_SRC_H2SEL_HW);
dmac_dev->dmac->lli[dmac_dev->chid].cfg |= DMAC_DST_H2SEL_SW | DMAC_SRC_H2SEL_HW;
/* Setup link list */
for (i = 0; i < blknum; i++) {
/* Set Source and address transfer size and modulo operation */
dmac_dev->lli[i].ctrla = ((dmac_dev->blksz/4) & 0xffff)
| SRC_WIDTH(2) | DST_WIDTH(2) | SCSIZE;
dmac_dev->lli[i].ctrlb = DMAC_FC_PER2MEM | FLAG_SRC_INCREMENT
| FLAG_DST_INCREMENT | SET_DST_DSCR;
dmac_dev->lli[i].saddr = dmac_dev->io_addr;
dmac_dev->lli[i].daddr = paddr + dmac_dev->blksz * i;
if (i == blknum - 1)
/* Set last lli descriptor to 0 to mark NULL */
dmac_dev->lli[i].dscr = 0;
else
/* Set next lli descriptor */
dmac_dev->lli[i].dscr = lli_mphy + (i + 1) * lli_size;
}
} else if (dir == DATA_WRITE) { /* Block WRITE */
/* Setup DMA direction */
dmac_dev->dmac->lli[dmac_dev->chid].cfg &= ~(DMAC_DST_H2SEL_HW | DMAC_SRC_H2SEL_SW);
dmac_dev->dmac->lli[dmac_dev->chid].cfg |= DMAC_DST_H2SEL_HW | DMAC_SRC_H2SEL_SW;
for (i = 0; i < blknum; i++) {
/* Set Source and address transfer size and modulo operation */
dmac_dev->lli[i].ctrla = ((dmac_dev->blksz/4) & 0xffff)
| SRC_WIDTH(2) | DST_WIDTH(2) | DCSIZE;
dmac_dev->lli[i].ctrlb = DMAC_FC_MEM2PER | FLAG_SRC_INCREMENT
| FLAG_DST_INCREMENT | SET_SRC_DSCR;
dmac_dev->lli[i].saddr = paddr + dmac_dev->blksz * i;
dmac_dev->lli[i].daddr = dmac_dev->io_addr;
if (i == blknum - 1)
/* Set last lli descriptor to 0 to mark NULL */
dmac_dev->lli[i].dscr = 0;
else
/* Set next lli descriptor */
dmac_dev->lli[i].dscr = lli_mphy + (i + 1) * lli_size;
}
} else {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMA setup_xfer neither READ or WRITE\n");
return -1;
}
return 0;
}
static void mmc_disp_mmc_cid(uint8_t mmc_prot, mmc_cid_t *cid)
{
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, "MMC CID info:");
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " MID (Manufacturer ID) : %d", cid->mid);
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " PNM (Product name) : %s", cid->pnm);
if (mmc_prot < 2) {
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " HWR (Hardware revision) : %d", cid->hwr);
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " FWR (Hardware revision) : %d", cid->fwr);
} else
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " OID (OEM ID) : %d", cid->oid);
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " PSN (Product serial number) : %08x", cid->psn);
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " MCD (Month code) : %d", cid->mcd);
slogf(_SLOGC_SIM_MMC, _SLOG_INFO, " YCD (Year code) : %d", cid->ycd);
}
static void
termination_hndlr(int sig_num)
{
char * pMsgTxt = "Hit with signal: %d, shutting down\n";
if(verbosity)
fprintf(stderr, pMsgTxt, sig_num);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt, sig_num);
input_shutdown();
}
int
omap_clock_toggle_init(DEV_OMAP* dev)
{
if (OMAP_UART1_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART1_CLKCTRL;
} else if (OMAP_UART2_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART2_CLKCTRL;
} else if (OMAP_UART3_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART3_CLKCTRL;
} else if (OMAP_UART4_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART4_CLKCTRL;
} else if (OMAP5_UART5_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART5_CLKCTRL;
} else if (OMAP5_UART6_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART6_CLKCTRL;
} else {
dev->clkctrl_phys = 0;
dev->clkctrl_base = 0;
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: Unrecognized physical address, clock toggling not enabled", __FUNCTION__);
return -1;
}
if (dev->clkctrl_phys) {
dev->clkctrl_base = mmap_device_io(4, dev->clkctrl_phys);
if (dev->clkctrl_base == (uintptr_t)MAP_FAILED) {
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: mmap_device_io clkctrl_base: %s", __FUNCTION__, strerror(errno));
return -1;
}
}
/* Indicate clocks are disabled by default */
dev->idle = 1;
/* oband notification set to off */
dev->signal_oband_notification = 0;
/* initialize UART context */
omap_uart_ctx_init(dev);
return 0;
}
/* Comment : Must be called before any other devi_usb... function */
void devi_usb_init()
{
LIST_INIT(&modList);
pGlbConnection = NULL;
if(EOK != pthread_mutex_init(&mod_mutex, NULL))
{
char * pMsgTxt = "Error: USB stack initialization error. Driver is terminating\n";
fprintf(stderr, pMsgTxt);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt);
exit(-1);
}
}
static int _omap_ienable(void *hdl, int enable)
{
omap3_ext_t *ctx = (omap3_ext_t *)hdl;
uintptr_t base = ctx->mmc_base;
/* Note: This can be called from an interrupt isr */
//InterruptDisable();
if (enable) {
_out32(base + OMAP3_MMCHS_IE,_in32(base + OMAP3_MMCHS_IE) & ~INTR_CIRQ);
_out32(base + OMAP3_MMCHS_ISE,_in32(base + OMAP3_MMCHS_ISE) | INTR_CIRQ);
_out32(base + OMAP3_MMCHS_IE, _in32(base + OMAP3_MMCHS_IE) | INTR_CIRQ);
DEBUG_CMD(slogf(99,1,"%s ise %x ie %x stat %x", __FUNCTION__, _in32(base + OMAP3_MMCHS_ISE), _in32(base + OMAP3_MMCHS_IE), _in32(base + OMAP3_MMCHS_STAT));)
} else {
void
omap_clock_disable(DEV_OMAP* dev)
{
int rc = 0;
/* Our idle state can be changed by the ISR so we must use a spinlock */
InterruptLock(&dev->idle_spinlock);
/* Only disable clocks if needed */
if (dev->idle == 1) {
goto done;
}
if (dev->clkctrl_base) {
/* Indicate clocks are disabled */
dev->idle = 1;
/* Save UART context */
omap_uart_ctx_save(dev);
/* Set the idle mode to smart idle with wake up */
write_omap(dev->port[OMAP_UART_SYSC], OMAP_UART_SYSC_IDLEMODE_SMARTWAKEUP |
OMAP_UART_SYSC_ENAWAKEUP_ENABLE |
OMAP_UART_SYSC_AUTOIDLE_ENABLE);
/* Enable the wakeup event */
set_port(dev->port[OMAP_UART_SCR], OMAP_SCR_WAKEUPEN, OMAP_SCR_WAKEUPEN);
/* Disable the clock */
out32(dev->clkctrl_base, OMAP_CLKCTRL_MODMODE_DISABLE);
/* Wait for the module mode to have been written */
rc = poll_for_condition(dev->clkctrl_base, OMAP_CLKCTRL_MODMODE_MASK, OMAP_CLKCTRL_MODMODE_DISABLE);
}
done:
InterruptUnlock(&dev->idle_spinlock);
/* Don't slog while interrupts are disabled - otherwise slogf() will re-enable interrupts */
if (rc) {
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: Failed to set module mode to 'disabled'", __FUNCTION__);
}
}
int twl4030_setup_graphics(disp_adapter_t *adapter)
{
unsigned speed;
int err;
/*
* Open the I2C controller device for the codec
*/
fd = open(TWL4030_I2C_DEVICE, O_RDWR);
if (fd == NULL) {
perror("open");
return -1;
}
printf("\n Setting up graphics \n");
slogf(21,0,"setting up graphics \n" );
/*
* Set the I2C speed for the codec
*/
speed = TWL4030_I2C_SPEED;
err = devctl(fd, DCMD_I2C_SET_BUS_SPEED, &speed, sizeof(speed), NULL);
if (err != EOK) {
return -1;
}
/* turn on LCD backlight */
//twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x33);
//twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_LEDEN, 0x32);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMAON, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMAOFF, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMBON, 0x7F);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP2, TWL4030_PWMBOFF, 0x7F);
/* configure VPLL2 for graphics */
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEDICATED, TWL4030_ENABLE_VAUX4_DEDICATED);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VAUX4_DEV_GRP, TWL4030_ENABLE_VAUX4_DEV_GRP);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEDICATED, TWL4030_ENABLE_VPLL2_DEDICATED);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP1, TWL4030_VPLL2_DEV_GRP, TWL4030_ENABLE_VPLL2_DEV_GRP);
return 0;
}
/* devices ( see devi_register_hid_client) */
int devi_usb_server_connect(char * serv_path_name)
{
int rc = EOK;
usbd_funcs_t funcs = { _USBDI_NFUNCS, insertion, removal, NULL };
usbd_device_ident_t interest = { USBD_CONNECT_WILDCARD, USBD_CONNECT_WILDCARD, USBD_CONNECT_WILDCARD, USBD_CONNECT_WILDCARD, USBD_CONNECT_WILDCARD };
usbd_connect_parm_t parm = { NULL, USB_VERSION, USBD_VERSION, 0, 0, NULL, 0, &interest, &funcs, USBD_CONNECT_WAIT };
parm.path = serv_path_name;
if(EOK != ( rc = usbd_connect( &parm, &pGlbConnection ) ) )
{
char * pMsgTxt = "Error: cannot connect to USB server (error code = %d).\nDriver is terminating\n";
fprintf(stderr, pMsgTxt, rc);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt, rc);
exit(-2);
}
return EOK;
}
int bs_init(SIM_HBA *hba)
{
SIM_MMC_EXT *ext;
omap3_ext_t *omap;
CONFIG_INFO *cfg;
beagle_ext_t *beagle;
unsigned gpiobase;
char machine_name[MACHINE_NAME_MAX_LEN];
if ((beagle = calloc(1, sizeof(beagle_ext_t))) == NULL)
return MMC_FAILURE;
cfg = (CONFIG_INFO *) &hba->cfg;
if (!cfg->NumIOPorts)
{
cfg->IOPort_Base[0] = OMAP3_MMCHS1_BASE;
cfg->IOPort_Length[0] = OMAP3_MMCHS_SIZE;
cfg->IOPort_Base[1] = OMAP3_DMA4_BASE;
cfg->IOPort_Length[1] = OMAP3_DMA4_SIZE;
cfg->NumIOPorts = 2;
}
else if (cfg->NumIOPorts < 2)
{
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "OMAP3 MMCSD: DMA4 base address must be specified");
return MMC_FAILURE;
}
if (!cfg->NumIRQs)
{
cfg->IRQRegisters[0] = OMAP3_MMCHS1_IRQ;
cfg->NumIRQs = 1;
}
if (!cfg->NumDMAs)
{
cfg->DMALst[0] = (DMA4_MMC1_TX >> 1) & 0xFF;
cfg->DMALst[1] = DMA4_MMC1_TX; // DMA request line for MMC1 TX
cfg->DMALst[2] = DMA4_MMC1_RX; // DMA request line for MMC1 RX
cfg->NumDMAs = 3;
}
int twl4030_enable_dvi(disp_adapter_t *adapter)
{
unsigned speed;
unsigned char b;
int err;
/*
* Open the I2C controller device for the codec
*/
fd = open(TWL4030_I2C_DEVICE, O_RDWR);
if (fd == NULL) {
perror("open");
return -1;
}
printf("\n Enable DVI output on BeagleBoard-xM\n");
slogf(21,0,"Enable DVI output on BeagleBoard-xM\n" );
/*
* Set the I2C speed for the codec
*/
speed = TWL4030_I2C_SPEED;
err = devctl(fd, DCMD_I2C_SET_BUS_SPEED, &speed, sizeof(speed), NULL);
if (err != EOK) {
return -1;
}
/* Set GPOI2 (DVI_PU) high, to power on the DVI */
// First set the direction. Read in the existing direction value
if (twl4030_i2c_read(TWL4030_ADDR_GRP4, 0x9B, &b))
return -1; // bail if the access fails
b |= (1 << 2);
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP4, 0x9B, b);
// Now set the value high
twl4030_i2c_write(adapter, TWL4030_ADDR_GRP4, 0xA4, (unsigned char)(1<<2));
return 0;
}
static int
remove_ocb(devi_attr_t *attr, RESMGR_OCB_T *ocb)
{
struct _ocb_list *op;
for (op = attr->ocb_list; op; op = op->next) {
if (op->ocb == ocb)
break;
}
if (op == NULL) {
char * pMsgTxt = "Error: nable to remove ocb from list, not found\n";
fprintf(stderr, pMsgTxt);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt);
return (-1);
}
/* If removing first one */
if (op->prev == NULL) {
if (op->next) {
attr->ocb_list = op->next;
op->next->prev = NULL;
}
else {
attr->ocb_list = NULL;
}
}
else {
if (op->next) {
op->prev->next = op->next;
op->next->prev = op->prev;
}
else
op->prev->next = NULL;
}
return (0);
}
static int twl4030_i2c_write(int fd, uint8_t addr, uint8_t reg, uint8_t val)
{
iov_t siov[3];
i2c_send_t hdr;
hdr.slave.addr = addr;
hdr.slave.fmt = I2C_ADDRFMT_7BIT;
hdr.len = 2;
hdr.stop = 1;
SETIOV(&siov[0], &hdr, sizeof(hdr));
SETIOV(&siov[1], ®, sizeof(reg));
SETIOV(&siov[2], &val, 1);
if (devctlv(fd, DCMD_I2C_SEND, 3, 0, siov, NULL, NULL) != EOK)
{
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "BEAGLE MMCSD: twl4030_i2c_write fail");
return -1;
}
return 0;
}
static void *timer_thread( void *p )
{
int pool_id;
int ret;
uint64_t clk;
uint64_t rdata;
int timeout;
ret = yarrow_add_source( Yarrow, &pool_id );
if( ret != 0 )
{
slogf( _SLOGC_CHAR, _SLOG_CRITICAL,
"random: Unable to get pool_id for timer thread." );
return NULL;
}
timeout = 100;
rdata = 0;
while( 1 )
{
if( Yarrow )
{
yarrow_output( Yarrow, (uint8_t *)&rdata, sizeof( rdata ) );
/* Wait for between 10ms and 1033ms */
timeout = ( rdata & 0x3FF ) + 10;
}
delay( timeout );
clk = ClockCycles();
clk = clk ^ rdata;
if( Yarrow )
yarrow_input( Yarrow, (uint8_t *)&clk, sizeof( clk ), pool_id, 8 );
}
return NULL;
}
static void dmac_fini (dmac_dev_t * dmac_dev)
{
rsrc_request_t req;
int timeout = 0;
munmap (dmac_dev->lli, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t) );
/* Disable channel */
dmac_dev->dmac->chdr |= (1 << dmac_dev->chid);
while (dmac_dev->dmac->chsr & (1 <<dmac_dev->chid)) {
delay (1);
if (timeout++ > TIMEOUT_LOOPS) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: release DMAC channel time out\n", __func__);
break;
}
}
/* release DMAC mmap resources */
munmap (dmac_dev->lli, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t) );
/* Release DMAC channel */
memset(&req, 0, sizeof(req));
req.length = 1;
req.flags = RSRCDBMGR_DMA_CHANNEL;
req.start = dmac_dev->chid;
req.end = dmac_dev->chid;
/* Return the resource to the database: */
rsrcdbmgr_detach( &req, 1);
if (dmac_dev != NULL) {
if ( dmac_dev->dmac!= MAP_FAILED)
munmap_device_memory((void *)dmac_dev->dmac, sizeof(at91sam9xx_dmac_t));
free (dmac_dev);
}
}
static int mpc5125_set_clock (mpc5125_ext_t *ext, int divisor)
{
mpc5125_mmc_reg *mmc = (mpc5125_mmc_reg *) ext->mmc_base;
int to;
if (mmc->sd_status & 0x100) {
mmc->sd_str_stp_clk = 1;
for (to = MPC5125_MMC_TMOUT; to > 0; to--) {
if ((mmc->sd_status & 0x100) == 0)
break;
nanospin_ns(100);;
}
if (to == 0) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mpc5125_set_clock(): timeout to get SD clock stopped");
return -1;
}
}
if (divisor < 8) {
divisor = 0x80;
}
mmc->sd_clk_rate = divisor;
mmc->sd_str_stp_clk = 2;
for (to = MPC5125_MMC_TMOUT; to > 0; to--) {
if (mmc->sd_status & 0x100) {
return (MMC_SUCCESS);
}
nanospin_ns(100);;
}
return (-1);
}
TProxy* tproxy_new(int argc, char* argv[], TProxyLogFunc slogf) {
assert(slogf);
in_addr_t inaddr = 0,
outaddr = 0,
traceaddr = 0;
char *hostname_bind,
*hostname_connect,
*hostname_trace;
char *inport,
*outport,
*traceport;
char *tmp;
if(argc < 4) {
slogf(G_LOG_LEVEL_WARNING, __FUNCTION__, USAGE);
return NULL;
}
asprintf(&tmp, "%s", argv[1]);
hostname_bind = strsep(&tmp, ":");
inport = tmp;
asprintf(&tmp, "%s", argv[2]);
hostname_connect = strsep(&tmp, ":");
outport = tmp;
asprintf(&tmp, "%s", argv[3]);
hostname_trace = strsep(&tmp, ":");
traceport = tmp;
printf("\t%s %s %s %s\n", hostname_bind, inport , hostname_connect, outport);
char myhostname[1024];
gethostname(myhostname, 1024);
slogf(G_LOG_LEVEL_MESSAGE, __FUNCTION__,
"myhostname %s", myhostname);
/* use epoll to asynchronously watch events for all of our sockets */
int inputEd = epoll_create(MAX_CLIENTS);
if(inputEd == -1) {
slogf(G_LOG_LEVEL_CRITICAL, __FUNCTION__,
"Error in main epoll_create");
close(inputEd);
return NULL;
}
/* DNS query */
/* get the address in network order */
inaddr = dnsQuery(hostname_bind);
outaddr = dnsQuery(hostname_connect);
traceaddr = dnsQuery(hostname_trace);
/* get memory for the new state */
TProxy* h = calloc(1, sizeof(TProxy));
assert(h);
h->outport = htons(atoi(outport));
h->inport = htons(atoi(inport));
h->traceport = htons(atoi(traceport));
h->ined = inputEd;
h->slogf = slogf;
h->isDone = 0;
h->hostIP = inaddr;
h->remoteIP = outaddr;
h->traceIP = traceaddr;
h->hashmap = g_hash_table_new(g_int_hash, g_int_equal);
h->serverMode = 0;
prepareToTrace(argc, argv, h);
/* extract the server hostname from argv if in client mode */
int isFail = 0;
isFail = _tproxy_startTProxy(h);
if(isFail) {
tproxy_free(h);
return NULL;
} else {
return h;
}
}
int hsmci_init (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci = NULL;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hba->verbosity = 4;
if (!ext->opts) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: missing board-specific options\n");
goto ARGSERR;
}
if ((hsmci = calloc(1, sizeof(hsmci_ext_t))) == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: alloc memory failed\n");
goto ERR;
}
cfg->MemLength[0] = 0x1000;
cfg->NumMemWindows = 1;
cfg->MemBase[0] = cfg->IOPort_Base[0];
base = (uintptr_t)mmap_device_memory(NULL, cfg->MemLength[0],
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, cfg->MemBase[0]);
if (base == (uintptr_t)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
hsmci->clock = 133000000;
hsmci->base = base;
hsmci->hba = hba;
ext->handle = hsmci;
ext->clock = hsmci->clock;
ext->detect = _hsmci_detect;
ext->powerup = _hsmci_powerup;
ext->powerdown = _hsmci_powerdown;
ext->cfg_bus = _hsmci_cfg_bus;
ext->set_clock = _hsmci_clock;
ext->set_blksz = _hsmci_block_size;
ext->interrupt = _hsmci_interrupt;
ext->command = _hsmci_command;
ext->setup_dma = _hsmci_setup_dma;
ext->dma_done = _hsmci_dma_done;
ext->setup_pio = _hsmci_setup_pio;
ext->pio_done = _hsmci_pio_done;
ext->shutdown = _hsmci_shutdown;
/* Parse options */
hsmci->port = -1;
hsmci->blksz = BLK_LENGTH;
hsmci->slot = 0;
/* Hardcode DMAC controller base address according to G45 datasheet
* since this driver is specifically for G45 SoC */
hsmci->dbase = DMAC_BASE;
if (!ext->opts)
goto ARGSERR;
if (hsmci_args(hba, ext->opts) == -1)
goto ARGSERR;
/*
* Set Src/Dst Request peripheral identifier SRC_PER/DST_PER
* handshaking interface # according to Table 41-1 DMA Channel Definition
* According to datasheet Table 35-2, the I/O line of mci0_da0 is pa2.
* According to datasheet Table 35-2, the I/O line of mci1_da0 is pa23.
*/
if (hsmci->port == 0) {
hsmci->dintf = 0;
hsmci->da0_mask = (1<<2);
} else {
hsmci->dintf=13;
hsmci->da0_mask = (1<<23);
}
/* Map G45 PIOA for polling busy signal */
pioa_pdsr = (uint32_t *)mmap_device_memory(NULL, 4,
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, PIOA_PDSR);
if (pioa_pdsr == (uint32_t *)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
if ( (uintptr_t) MAP_FAILED == ( hsmci->pio_base = mmap_device_io( AT91SAM9G45_PIO_SIZE, AT91SAM9G45_PIOD_BASE ) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PIOD_PDSR failed" );
goto ERR;
}
/* Configure CD and WP PIO */
InterruptDisable();
#define CFG_PIO(reg) out32( hsmci->pio_base + (reg), AT91SAM9G45_MCI_PIO_BITS )
CFG_PIO( AT91SAM9G45_PIO_PER ); /* Ensable PIO */
CFG_PIO( AT91SAM9G45_PIO_ODR ); /* Disable output */
CFG_PIO( AT91SAM9G45_PIO_IFDR ); /* Disable glitch input filter */
CFG_PIO( AT91SAM9G45_PIO_CODR ); /* Clear output data */
CFG_PIO( AT91SAM9G45_PIO_IDR ); /* Disable interrupt */
CFG_PIO( AT91SAM9G45_PIO_MDDR ); /* Disable multi-driver */
CFG_PIO( AT91SAM9G45_PIO_PUER ); /* Enable pull-up */
CFG_PIO( AT91SAM9G45_PIO_OWDR ); /* Output write disable */
#undef CFG_PIO
InterruptEnable();
/* Configure capacity of controller */
ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS;
// Use the flag MMC_HCCAP_NOCD_BUSY to inform the MMCSD stack that this hardware has R1B bug
// ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS | MMC_HCCAP_NOCD_BUSY;
/* Disable the controller and soft reset */
WRITE32(MCI_CR, SWRST | PWSDIS);
delay (100);
WRITE32(MCI_CR, MCIDIS | PWSDIS);
/* Disable DMA */
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
/* Enable the controller */
WRITE32(MCI_CR, MCIEN | PWSDIS);
WRITE32(MCI_IDR, 0xffffffff);
/* Set Timeout to Max */
WRITE32(MCI_DTOR, 0x7f);
/* Use the lowest baudrate */
WRITE32 (MCI_MR, 0xff | WRPROOF| RDPROOF);
hsmci->dmac_dev = dmac_init(hsmci);
if (hsmci->dmac_dev == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: dmafuncs init FAILED\n");
goto ERR;
}
hsmci->dmac_dev->io_addr = cfg->MemBase[0] + MCI_FIFO;
hsmci->dmac_dev->blksz = hsmci->blksz;
/* Select slot, set bus to 1 bit */
WRITE32 (MCI_SDCR, hsmci->slot);
if (!cfg->Description[0])
strncpy(cfg->Description, "Atmel HSMCI ", sizeof(cfg->Description));
if ( (uintptr_t) MAP_FAILED == ( hsmci->pmc_base = mmap_device_io(PMC_SIZE, PMC_BASE) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PMC failed" );
goto ERR;
}
return (MMC_SUCCESS);
ARGSERR:
printf("\nImproper board-specific options used. Accepting args: \n");
printf(" port=# The MCI port been used (0 or 1)\n");
printf("NOTE:\n");
printf(" 1. The args are seperated by colon ':'\n");
printf("Example:\n");
printf("at91sam9g45 port 0: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFF80000,irq=11,bs=port=0\n");
printf("at91sam9g45 port 1: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFFD0000,irq=29,bs=port=1\n");
ERR:
if (hsmci) {
munmap_device_memory ((void *)hsmci->base, (uint32_t)cfg->MemLength[0]);
if (hsmci->pio_base)
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
free (hsmci);
}
if (pioa_pdsr != (uint32_t *)MAP_FAILED)
munmap_device_memory ((void *)pioa_pdsr, 4);
return (MMC_FAILURE);
}
static int omap3_interrupt(SIM_HBA *hba, int irq, int resp_type, uint32_t *resp)
{
SIM_MMC_EXT *ext;
omap3_ext_t *omap3;
uint32_t sts;
int intr = 0;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
omap3 = (omap3_ext_t *)ext->handle;
base = omap3->mmc_base;
sts = in32(base + OMAP3_MMCHS_STAT);
sts &= in32(base + OMAP3_MMCHS_IE) | INTR_ERRI;
out32(base + OMAP3_MMCHS_STAT, sts);
if (sts & INTR_ERRI) { // Any errors ?
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "OMAP3 interrupt error = %x", sts);
intr |= MMC_INTR_ERROR | MMC_INTR_COMMAND;
if (sts & INTR_DTO) {
intr |= MMC_ERR_DATA_TO;
out32(base + OMAP3_MMCHS_SYSCTL, in32(base + OMAP3_MMCHS_SYSCTL) | SYSCTL_SRD);
while (in32(base + OMAP3_MMCHS_SYSCTL) & SYSCTL_SRD);
}
if (sts & INTR_DCRC)
intr |= MMC_ERR_DATA_CRC;
if (sts & INTR_DEB)
intr |= MMC_ERR_DATA_END;
if (sts & INTR_CTO) {
intr |= MMC_ERR_CMD_TO;
out32(base + OMAP3_MMCHS_SYSCTL, in32(base + OMAP3_MMCHS_SYSCTL) | SYSCTL_SRC);
while (in32(base + OMAP3_MMCHS_SYSCTL) & SYSCTL_SRC);
}
if (sts & INTR_CCRC)
intr |= MMC_ERR_CMD_CRC;
if (sts & INTR_CEB)
intr |= MMC_ERR_CMD_END;
if (sts & INTR_CIE)
intr |= MMC_ERR_CMD_IDX;
} else {
if (sts & INTR_CC) {
intr |= MMC_INTR_COMMAND;
if (resp) {
if (resp_type & MMC_RSP_136) {
resp[3] = in32(base + OMAP3_MMCHS_RSP76);
resp[2] = in32(base + OMAP3_MMCHS_RSP54);
resp[1] = in32(base + OMAP3_MMCHS_RSP32);
resp[0] = in32(base + OMAP3_MMCHS_RSP10);
} else if (resp_type & MMC_RSP_PRESENT)
resp[0] = in32(base + OMAP3_MMCHS_RSP10);
}
// Busy check?
if (resp_type & MMC_RSP_BUSY) {
int i;
for (i = 1024 * 256; i > 0; i--) {
if (in32(base + OMAP3_MMCHS_PSTATE) & PSTATE_DLA) {
nanospin_ns(1024);
continue;
}
break;
}
if (i <= 0) {
intr |= MMC_ERR_CMD_TO | MMC_INTR_ERROR;
slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "OMAP3 busy check time out");
}
}
}
if (sts & (INTR_TC | INTR_BWR | INTR_BRR)) {
if (sts & INTR_TC)
intr |= MMC_INTR_DATA;
if (sts & INTR_BRR)
intr |= MMC_INTR_RBRDY;
if (sts & INTR_BWR)
intr |= MMC_INTR_WBRDY;
}
}
if (intr)
out32(base + OMAP3_MMCHS_IE, 0);
return intr;
}
DEV_OMAP *
create_device(TTYINIT_OMAP *dip, unsigned unit, unsigned maxim_xcvr_kick) {
DEV_OMAP *dev;
unsigned i;
uintptr_t port;
unsigned char msr;
unsigned char tlr = 0, tcr = 0;
#ifdef PWR_MAN
clk_enable_t clk_cfg = clk_enable_none;
#endif
// Get a device entry and the input/output buffers for it.
if ((dev = malloc(sizeof(*dev))) == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of device entry failed (%d)", errno);
return (dev);
}
memset(dev, 0, sizeof(*dev));
// Get buffers.
dev->tty.ibuf.head = dev->tty.ibuf.tail = dev->tty.ibuf.buff = malloc(dev->tty.ibuf.size = dip->tty.isize);
if (dev->tty.ibuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of input buffer failed (%d)", errno);
free(dev);
return (NULL);
}
dev->tty.obuf.head = dev->tty.obuf.tail = dev->tty.obuf.buff = malloc(dev->tty.obuf.size = dip->tty.osize);
if (dev->tty.obuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of output buffer failed (%d)", errno);
free(dev->tty.ibuf.buff);
free(dev);
return (NULL);
}
dev->tty.cbuf.head = dev->tty.cbuf.tail = dev->tty.cbuf.buff = malloc(dev->tty.cbuf.size = dip->tty.csize);
if (dev->tty.cbuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of canonical buffer failed (%d)", errno);
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
if (dip->tty.highwater)
dev->tty.highwater = dip->tty.highwater;
else
dev->tty.highwater = dev->tty.ibuf.size - (FIFO_SIZE * 2);
strcpy(dev->tty.name, dip->tty.name);
dev->tty.baud = dip->tty.baud;
dev->tty.fifo = dip->tty.fifo;
dev->tty.verbose = dip->tty.verbose;
port = mmap_device_io(OMAP_UART_SIZE, dip->tty.port);
for (i = 0; i < OMAP_UART_SIZE; i += 4)
dev->port[i] = port + i;
dev->intr = dip->tty.intr;
dev->clk = dip->tty.clk;
dev->div = dip->tty.div;
dev->tty.flags = EDIT_INSERT | LOSES_TX_INTR;
dev->tty.c_cflag = dip->tty.c_cflag;
dev->tty.c_iflag = dip->tty.c_iflag;
dev->tty.c_lflag = dip->tty.c_lflag;
dev->tty.c_oflag = dip->tty.c_oflag;
dev->tty.lflags = dip->tty.lflags;
if (dip->tty.logging_path[0] != NULL)
dev->tty.logging_path = strdup(dip->tty.logging_path);
#ifdef PWR_MAN
dev->physbase = dip->tty.port;
if (omap_clock_toggle_init(dev) != EOK)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Fail to initialize clocks for PM!");
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
#ifdef WINBT
clk_cfg = clk_enable_smart_wkup;
if (omap_force_rts_init(dev) != EOK)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Fail to initialize force_rts for PM!");
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
#endif
omap_clock_enable(dev, clk_cfg);
#ifdef WINBT
bt_ctrl_init();
#endif
#endif
/* Set auto_rts mode */
dev->auto_rts_enable = dip->auto_rts_enable;
// Do not enable MSR interrupt
dev->no_msr_int = dip->no_msr_int;
// Initialize termios cc codes to an ANSI terminal.
ttc(TTC_INIT_CC, &dev->tty, 0);
// Initialize the device's name.
// Assume that the basename is set in device name. This will attach
// to the path assigned by the unit number/minor number combination
unit = SET_NAME_NUMBER(unit) | NUMBER_DEV_FROM_USER;
ttc(TTC_INIT_TTYNAME, &dev->tty, unit);
// see if we have a maxim rs-232 transceiver that needs to be
// kicked after it goes to sleep
dev->kick_maxim = maxim_xcvr_kick;
// Only setup IRQ handler for non-pcmcia devices.
// Pcmcia devices will have this done later when card is inserted.
if (dip->tty.port != 0 && dip->tty.intr != _NTO_INTR_SPARE) {
#ifdef OMAP5910
/*
* Don't change default mode set in the very distant past. Even though
* MODE_SELECT should be DISABLE before changing DLH, DLL.
*/
// enable the UART
write_omap(dev->port[OMAP_UART_MDR1], OMAP_MDR1_MODE_16X);
#else
/*
* TRM states: Before initializing or modifying clock parameter controls
* (DLH, DLL), MODE_SELECT must be set to 0x7 (DISABLE). Failure to observe
* this rule can result in unpredictable module behavior.
*/
write_omap(dev->port[OMAP_UART_MDR1], OMAP_MDR1_MODE_DISABLE);
#endif
/* Work around for silicon errata i202 states: */
/* Need a delay = 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) */
nanospin_ns(200);
/* Clear FIFOs */
set_port(dev->port[OMAP_UART_FCR], OMAP_FCR_RXCLR | OMAP_FCR_TXCLR, OMAP_FCR_RXCLR | OMAP_FCR_TXCLR);
/* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and TX_FIFO_E bit is 1 */
i = 5;
while ((read_omap(dev->port[OMAP_UART_LSR]) & (OMAP_UART_LSR_THRE | OMAP_UART_LSR_DR)) != OMAP_UART_LSR_THRE)
{
nanospin_ns(200);
if (--i == 0)
{
break; /* No need to do anything drastic if FIFO is still not empty */
}
}
// enable access to divisor registers
write_omap(dev->port[OMAP_UART_LCR], OMAP_LCR_DLAB);
write_omap(dev->port[OMAP_UART_DLL], 0);
write_omap(dev->port[OMAP_UART_DLH], 0);
/* Switch to config mode B to get access to EFR Register */
write_omap(dev->port[OMAP_UART_LCR], 0xBF);
/* Enable access to TLR register */
set_port(dev->port[OMAP_UART_EFR], OMAP_EFR_ENHANCED, OMAP_EFR_ENHANCED);
/* Switch to operational mode to get acces to MCR register */
write_omap(dev->port[OMAP_UART_LCR], 0x00);
/* set MCR bit 6 to enable access to TCR and TLR registers */
set_port(dev->port[OMAP_UART_MCR], OMAP_MCR_TCRTLR, OMAP_MCR_TCRTLR);
write_omap(dev->port[OMAP_UART_FCR], OMAP_FCR_ENABLE|OMAP_FCR_RXCLR|OMAP_FCR_TXCLR);
tcr = 0x0e; /* set auto-rts assert at 56 bytes, restore at 0 bytes */
if (dev->tty.fifo)
{
/* Set RX fifo trigger level */
switch (dev->tty.fifo >> 4) {
case FIFO_TRIG_8:
default:
tlr = 0x20;
break;
case FIFO_TRIG_16: tlr = 0x40; break;
case FIFO_TRIG_32: tlr = 0x80; break;
case FIFO_TRIG_56: tlr = 0xe0; break;
case FIFO_TRIG_60:
tlr = 0xf0;
tcr = 0x0f; /* Ensure auto-rts trigger is not less the RX trigger */
break;
}
/* Set TX fifo trigger level */
switch (dev->tty.fifo & 0x0f) {
case FIFO_TRIG_8:
default:
tlr |= 0x02;
break;
case FIFO_TRIG_16: tlr |= 0x04; break;
case FIFO_TRIG_32: tlr |= 0x08; break;
case FIFO_TRIG_56: tlr |= 0x0e; break;
case FIFO_TRIG_60: tlr |= 0x0f; break;
}
}
write_omap(dev->port[OMAP_UART_TCR], tcr);
write_omap(dev->port[OMAP_UART_TLR], tlr);
#ifdef PWR_MAN
write_omap(dev->port[OMAP_UART_SCR], OMAP_SCR_WAKEUPEN);
#else
write_omap(dev->port[OMAP_UART_SCR], 0x00);
#endif
/* Switch back to Config mode B to gain access to EFR again */
write_omap(dev->port[OMAP_UART_LCR], 0xBF);
/* remove access to TLR register */
set_port(dev->port[OMAP_UART_EFR], OMAP_EFR_ENHANCED, 0);
/* Switch to operational mode to get acces to MCR register */
write_omap(dev->port[OMAP_UART_LCR], 0x00);
/* clr MCR bit 6 to remove access to TCR and TLR registers */
set_port(dev->port[OMAP_UART_MCR], OMAP_MCR_TCRTLR, 0);
ser_stty(dev);
ser_attach_intr(dev);
}
TorFlowManager* torflowmanager_new(gint argc, gchar* argv[], ShadowLogFunc slogf, ShadowCreateCallbackFunc scbf) {
g_assert(slogf);
g_assert(scbf);
if(argc != 9) {
slogf(SHADOW_LOG_LEVEL_WARNING, __FUNCTION__, USAGE);
return NULL;
}
/* argv[0] is the 'program name' and should be ignored */
gchar* v3bwPath = argv[1];
gint pausetime = atoi(argv[2]);
gint numWorkers = atoi(argv[3]);
if(numWorkers < 1) {
slogf(SHADOW_LOG_LEVEL_WARNING, __FUNCTION__,
"Invalid number of torflow workers (%d). torflow will not operate.", numWorkers);
return NULL;
}
gint slicesize = atoi(argv[4]);
gdouble nodeCap = atof(argv[5]);
gint hostControlPort = atoi(argv[6]);
g_assert(hostControlPort <= G_MAXUINT16); // TODO log error instead
in_port_t netControlPort = htons((in_port_t)hostControlPort);
gint hostSocksPort = atoi(argv[7]);
g_assert(hostSocksPort <= G_MAXUINT16); // TODO log error instead
in_port_t netSocksPort = htons((in_port_t)hostSocksPort);
/* get file server infos */
GQueue* fileservers = g_queue_new();
gchar** fsparts = g_strsplit(argv[8], ",", 0);
gchar* fspart = NULL;
for(gint i = 0; (fspart = fsparts[i]) != NULL; i++) {
gchar** parts = g_strsplit(fspart, ":", 0);
g_assert(parts[0] && parts[1]);
/* the server domain name */
gchar* name = parts[0];
/* port in host order */
gchar* hostFilePortStr = parts[1];
gint hostFilePort = atoi(hostFilePortStr);
g_assert(hostFilePort <= G_MAXUINT16); // TODO log error instead
in_port_t netFilePort = htons((in_port_t)hostFilePort);
TorFlowFileServer* fs = torflowfileserver_new(name, netFilePort);
g_assert(fs);
g_queue_push_tail(fileservers, fs);
g_strfreev(parts);
slogf(SHADOW_LOG_LEVEL_INFO, __FUNCTION__,
"parsed file server %s at %s:%u",
torflowfileserver_getName(fs),
torflowfileserver_getHostIPStr(fs),
ntohs(torflowfileserver_getNetPort(fs)));
}
g_strfreev(fsparts);
g_assert(g_queue_get_length(fileservers) > 0); // TODO log error instead
/* use epoll to asynchronously watch events for all of our sockets */
gint mainEpollDescriptor = epoll_create(1);
g_assert(mainEpollDescriptor > 0); // TODO log error instead
TorFlowManager* tfm = g_new0(TorFlowManager, 1);
tfm->slogf = slogf;
tfm->scbf = scbf;
tfm->workers = numWorkers;
tfm->ed = mainEpollDescriptor;
tfm->slicesize = slicesize;
tfm->AllRelaysByFingerprint = g_hash_table_new_full(g_str_hash,
g_str_equal, NULL, (GDestroyNotify)_torflowmanager_freeRelay);
tfm->currentSlices = g_queue_new();
/* now start our controller to fetch descriptors */
tfm->baseED = epoll_create(1);
g_assert(tfm->baseED > 0); // TODO log error
torflowutil_epoll(tfm->ed, tfm->baseED, EPOLL_CTL_ADD, EPOLLIN, tfm->slogf);
TorFlowEventCallbacks handlers;
memset(&handlers, 0, sizeof(TorFlowEventCallbacks));
handlers.onBootstrapComplete = (BootstrapCompleteFunc) _torflowmanager_onBootstrapComplete;
handlers.onDescriptorsReceived = (DescriptorsReceivedFunc) _torflowmanager_onDescriptorsReceived;
torflowbase_init(&tfm->_base, &handlers, slogf, scbf, netControlPort, tfm->baseED, 0);
torflowbase_start(&tfm->_base);
/* helper to manage stat reports and create v3bw files */
tfm->tfa = torflowaggregator_new(slogf, v3bwPath, nodeCap);
/* workers that will probe the relays */
tfm->probers = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL, (GDestroyNotify) torflowbase_free);
for(gint i = 1; i <= numWorkers; i++) {
/* get the next fileserver */
TorFlowFileServer* probeFileServer = g_queue_pop_head(fileservers);
TorFlowProber* prober = torflowprober_new(slogf, scbf, tfm, i, numWorkers, pausetime,
netControlPort, netSocksPort, probeFileServer);
g_assert(prober); // TODO log error instead
/* make sure we watch the prober events on our main epoll */
gint proberED = torflow_getEpollDescriptor((TorFlow*)prober);
torflowutil_epoll(tfm->ed, proberED, EPOLL_CTL_ADD, EPOLLIN, tfm->slogf);
/* store the prober by its unique epoll descriptor */
g_hash_table_replace(tfm->probers, GINT_TO_POINTER(proberED), prober);
/* reuse the file server in round robin fashion */
g_queue_push_tail(fileservers, probeFileServer);
}
/* the used file servers have been reffed by the probers;
* the rest will be safely freed */
g_queue_free_full(fileservers, (GDestroyNotify)torflowfileserver_unref);
tfm->slogf(SHADOW_LOG_LEVEL_MESSAGE, __FUNCTION__,
"started torflow with %i workers on control port %i and socks port %i",
numWorkers, hostControlPort, hostSocksPort);
return tfm;
}
//
// this is a callback, made by the bsd media code. We passed
// a pointer to this function during the ifmedia_init() call
// in bsd_mii_initmedia(). This function is called when
// someone makes an ioctl into us, we call into the generic
// ifmedia source, and it make this callback to actually
// force the speed and duplex, just as if the user had
// set the cmd line options
//
int
bsd_mii_mediachange(struct ifnet *ifp)
{
ti814x_dev_t *ti814x = ifp->if_softc;
int old_media_rate = ti814x->cfg.media_rate;
int old_duplex = ti814x->cfg.duplex;
int old_force_link = ti814x->force_link;
struct ifmedia *ifm = &ti814x->bsd_mii.mii_media;
int user_duplex = ifm->ifm_media & IFM_FDX ? 1 : 0;
int user_media = ifm->ifm_media & IFM_TMASK;
if (!(ifp->if_flags & IFF_UP)) {
slogf(_SLOGC_NETWORK, _SLOG_WARNING,
"%s(): network interface isn't up, ioctl ignored", __FUNCTION__);
return 0;
}
if (!(ifm->ifm_media & IFM_ETHER)) {
slogf(_SLOGC_NETWORK, _SLOG_WARNING,
"%s(): network interface - bad media: 0x%X",
__FUNCTION__, ifm->ifm_media);
return 0; // should never happen
}
switch (user_media) {
case IFM_AUTO: // auto-select media
ti814x->force_link = 0;
ti814x->cfg.media_rate = -1;
ti814x->cfg.duplex = -1;
ifmedia_set(&ti814x->bsd_mii.mii_media, IFM_ETHER|IFM_AUTO);
break;
case IFM_NONE: // disable media
//
// forcing the link with a speed of zero means to disable the link
//
ti814x->force_link = 1;
ti814x->cfg.media_rate = 0;
ti814x->cfg.duplex = 0;
ifmedia_set(&ti814x->bsd_mii.mii_media, IFM_ETHER|IFM_NONE);
break;
case IFM_10_T: // force 10baseT
ti814x->force_link = 1;
ti814x->cfg.media_rate = 10 * 1000;
ti814x->cfg.duplex = user_duplex;
ifmedia_set(&ti814x->bsd_mii.mii_media,
user_duplex ? IFM_ETHER|IFM_10_T|IFM_FDX : IFM_ETHER|IFM_10_T);
break;
case IFM_100_TX: // force 100baseTX
ti814x->force_link = 1;
ti814x->cfg.media_rate = 100 * 1000;
ti814x->cfg.duplex = user_duplex;
ifmedia_set(&ti814x->bsd_mii.mii_media,
user_duplex ? IFM_ETHER|IFM_100_TX|IFM_FDX : IFM_ETHER|IFM_100_TX);
break;
case IFM_1000_T: // force 1000baseT
// only GigE full duplex supported
ti814x->force_link = 1;
ti814x->cfg.media_rate = 1000 * 1000;
ti814x->cfg.duplex = user_duplex;
ifmedia_set(&ti814x->bsd_mii.mii_media,
user_duplex ? IFM_ETHER|IFM_1000_T|IFM_FDX : IFM_ETHER|IFM_1000_T);
break;
default: // should never happen
slogf(_SLOGC_NETWORK, _SLOG_WARNING,
"%s(): network interface - unknown media: 0x%X",
__FUNCTION__, user_media);
return 0;
break;
}
// does the user want something different than it already is?
if ((ti814x->cfg.media_rate != old_media_rate) ||
(ti814x->cfg.duplex != old_duplex) ||
(ti814x->force_link != old_force_link) ||
(ti814x->cfg.flags & NIC_FLAG_LINK_DOWN) ) {
// re-initialize hardware with new parameters
ifp->if_init(ifp);
}
return 0;
}
int
resmgr_create_device(event_bus_line_t *line)
{
devi_attr_t *attr;
resmgr_attr_t res_attr;
static resmgr_connect_funcs_t connect_funcs;
static resmgr_io_funcs_t io_funcs;
static int once = 0;
int i;
char name[48];
char path[_POSIX_PATH_MAX];
int id;
dev_t d;
if ((attr = malloc(sizeof(devi_attr_t))) == NULL) {
errno_print("malloc");
return (-1);
}
if (!once) {
iofunc_func_init(_RESMGR_CONNECT_NFUNCS, &connect_funcs,
_RESMGR_IO_NFUNCS, &io_funcs);
connect_funcs.open = devi_open;
io_funcs.devctl = devi_devctl;
io_funcs.read = devi_read;
io_funcs.close_ocb = devi_close;
io_funcs.unblock = devi_unblock;
io_funcs.notify = devi_notify;
once = 1;
}
iofunc_attr_init(&attr->attr, 0666 | S_IFCHR, NULL, NULL);
attr->flags = line->type;
attr->ocb_list = NULL;
line->attr = attr;
switch (attr->flags) {
case DEVI_CLASS_KBD:
strcpy(name, "keyboard");
break;
case DEVI_CLASS_REL:
strcpy(name, "mouse");
break;
case DEVI_CLASS_ABS:
strcpy(name, "touch");
break;
}
attr->line = line;
memset(&res_attr, 0, sizeof(res_attr));
res_attr.msg_max_size = 2048;
res_attr.nparts_max = 3;
for (i = 0; i < 10; i++) {
sprintf(path, DEVICE_NAME, name, i);
if (access(path, F_OK) != 0)
break;
}
if (i == 10) {
char * pMsgTxt = "Error: unable to create device %s\n";
fprintf(stderr, pMsgTxt, path);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt, path);
free(attr);
return (-1);
}
id = resmgr_attach(devi_get_dispatch_handle(), &res_attr, path,
_FTYPE_ANY, 0, &connect_funcs,
&io_funcs, (void *) &attr->attr);
if (id < 0) {
char * pMsgTxt = "Error: could not attach resource manager\n";
fprintf(stderr, pMsgTxt);
slogf(_SLOG_SETCODE(_SLOGC_INPUT, 0), _SLOG_ERROR, pMsgTxt);
free(attr);
return (-1);
}
attr->attr.rdev = rsrcdbmgr_devno_attach(name, -1, 0);
resmgr_devino(id, &d, &attr->attr.inode);
return (0);
}
