void* platform_get_mmap(void* pdata, platform_mmap_cb_t cb) { uint32_t i; ram_partition part; // Make sure RAM partition table is initialized ASSERT(smem_ram_ptable_init_v1()); for(i=0; i<smem_get_ram_ptable_len(); i++) { smem_get_ram_ptable_entry(&part, i); if(part.category==SDRAM && part.type==SYS_MEMORY) { // patch first 256M if(part.start==PHYS_MEM_ADDR) { pdata = platform_mmap_report_first_256MB(pdata, cb); if (part.size > 256*MB) { pdata = cb(pdata, (paddr_t) part.start+256*MB, (size_t)part.size-256*MB, false); } } // Pass along all other usable memory regions to Linux else pdata = cb(pdata, (paddr_t) part.start, (size_t)part.size, false); } } return pdata; }
uint32_t get_ddr_start() { uint32_t i; ram_partition ptn_entry; uint32_t len = 0; ASSERT(smem_ram_ptable_init_v1()); len = smem_get_ram_ptable_len(); /* Determine the Start addr of the DDR RAM */ for(i = 0; i < len; i++) { smem_get_ram_ptable_entry(&ptn_entry, i); if(ptn_entry.type == SYS_MEMORY) { if((ptn_entry.category == SDRAM) || (ptn_entry.category == IMEM)) { /* Check to ensure that start address is 1MB aligned */ ASSERT((ptn_entry.start & (MB-1)) == 0); return ptn_entry.start; } } } ASSERT("DDR Start Mem Not found\n"); return 0; }
/* Setup memory for this platform */ void platform_init_mmu_mappings(void) { uint32_t i; uint32_t sections; ram_partition ptn_entry; uint32_t table_size = ARRAY_SIZE(mmu_section_table); uint32_t len = 0; ASSERT(smem_ram_ptable_init_v1()); len = smem_get_ram_ptable_len(); /* Configure the MMU page entries for SDRAM and IMEM memory read from the smem ram table*/ for(i = 0; i < len; i++) { smem_get_ram_ptable_entry(&ptn_entry, i); if(ptn_entry.type == SYS_MEMORY) { if((ptn_entry.category == SDRAM) || (ptn_entry.category == IMEM)) { /* Check to ensure that start address is 1MB aligned */ ASSERT((ptn_entry.start & (MB-1)) == 0); sections = (ptn_entry.size) / MB; while(sections--) { arm_mmu_map_section(ptn_entry.start + sections * MB, ptn_entry.start + sections * MB, (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)); } } } } /* Configure the MMU page entries for memory read from the mmu_section_table */ for (i = 0; i < table_size; i++) { sections = mmu_section_table[i].num_of_sections; while (sections--) { arm_mmu_map_section(mmu_section_table[i].paddress + sections * MB, mmu_section_table[i].vaddress + sections * MB, mmu_section_table[i].flags); } } }
uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset) { ram_partition ptn_entry; unsigned int index; int ret = 0; uint32_t len = 0; /* Make sure RAM partition table is initialized */ ASSERT(smem_ram_ptable_init_v1()); len = smem_get_ram_ptable_len(); /* Calculating the size of the mem_info_ptr */ for (index = 0 ; index < len; index++) { smem_get_ram_ptable_entry(&ptn_entry, index); if((ptn_entry.category == SDRAM) && (ptn_entry.type == SYS_MEMORY)) { /* Pass along all other usable memory regions to Linux */ ret = dev_tree_add_mem_info(fdt, memory_node_offset, ptn_entry.start, ptn_entry.size); if (ret) { dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n"); goto target_dev_tree_mem_err; } } } target_dev_tree_mem_err: return ret; }