static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ relo_attrs.smbase = (uint32_t)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; *perm_smbase = relo_attrs.smbase; *perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); }
static int smm_load_handlers(void) { /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); const struct pattrs *pattrs = pattrs_get(); /* Initialize global tracking state. */ relo_attrs.smbase = (uint32_t)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); return -1; } if (install_permanent_handler(pattrs->num_cpus) < 0) { printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); return -1; } /* Ensure the SMM handlers hit DRAM before performing first SMI. */ wbinvd(); return 0; }
struct ramstage_cache *ramstage_cache_location(long *size) { /* The ramstage cache lives in the TSEG region. * The top of ram is defined to be the TSEG base address. */ u32 offset = smm_region_size(); offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; *size = CONFIG_SMM_RESERVED_SIZE; return (void *)(cbmem_top() + offset); }
void stage_cache_external_region(void **base, size_t *size) { char *smm_base; /* 1MiB cache size */ const long cache_size = CONFIG_SMM_RESERVED_SIZE; /* Ramstage cache lives in TSEG region which is the definition of * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; *base = &smm_base[smm_region_size() - cache_size]; }
struct ramstage_cache *ramstage_cache_location(long *size) { char *smm_base; /* 1MiB cache size */ const long cache_size = CONFIG_SMM_RESERVED_SIZE; /* Ramstage cache lives in TSEG region which is the definition of * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; return (void *)&smm_base[smm_region_size() - cache_size]; }
static int install_relocation_handler(int num_cpus) { const int save_state_size = sizeof(em64t100_smm_state_save_area_t); struct smm_loader_params smm_params = { .per_cpu_stack_size = save_state_size, .num_concurrent_stacks = num_cpus, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = 1, .handler = (smm_handler_t)&cpu_smm_do_relocation, }; if (smm_setup_relocation_handler(&smm_params)) return -1; adjust_apic_id_map(&smm_params); return 0; } static int install_permanent_handler(int num_cpus) { #ifndef CONFIG_SMM_RESERVED_SIZE #error CONFIG_SMM_RESERVED_SIZE must be set. #endif /* There are num_cpus concurrent stacks and num_cpus concurrent save * state areas. Lastly, set the stack size to the save state size. */ int save_state_size = sizeof(em64t100_smm_state_save_area_t); struct smm_loader_params smm_params = { .per_cpu_stack_size = save_state_size, .num_concurrent_stacks = num_cpus, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = num_cpus, }; const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", relo_attrs.smbase); if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) return -1; adjust_apic_id_map(&smm_params); return 0; }
void broadwell_fill_pei_data(struct pei_data *pei_data) { pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; pei_data->usbdebug = CONFIG_USBDEBUG; pei_data->pciexbar = MCFG_BASE_ADDRESS; pei_data->smbusbar = SMBUS_BASE_ADDRESS; pei_data->ehcibar = EARLY_EHCI_BAR; pei_data->xhcibar = EARLY_XHCI_BAR; pei_data->gttbar = EARLY_GTT_BAR; pei_data->pmbase = ACPI_BASE_ADDRESS; pei_data->gpiobase = GPIO_BASE_ADDRESS; pei_data->tseg_size = smm_region_size(); pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; pei_data->ddr_refresh_2x = 1; }
size_t mmap_region_granluarity(void) { /* Align to TSEG size when SMM is in use, and 8MiB by default */ return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size() : 8 << 20; }
void smm_region(void **start, size_t *size) { *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); *size = smm_region_size(); }
void smm_region(void **start, size_t *size) { *start = (void *)smm_region_start(); *size = smm_region_size(); }
/** * Update the UPD data based on values from devicetree.cb * * @param UpdData Pointer to the UPD Data structure */ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { ROMSTAGE_CONST struct device *dev; ROMSTAGE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); dev = dev_find_slot(0, SOC_DEV_FUNC); config = dev->chip_info; /* Set up default verb tables - Just HDMI audio */ UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; /* Set SPD addresses */ UPD_SPD_CHECK(PcdMrcInitSPDAddr1); UPD_SPD_CHECK(PcdMrcInitSPDAddr2); UPD_DEFAULT_CHECK(PcdSataMode); UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode); UPD_DEFAULT_CHECK(PcdMrcInitMmioSize); UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc); UPD_DEFAULT_CHECK(PcdApertureSize); UPD_DEFAULT_CHECK(PcdGttSize); UPD_DEFAULT_CHECK(SerialDebugPortAddress); UPD_DEFAULT_CHECK(SerialDebugPortType); UPD_DEFAULT_CHECK(PcdMrcDebugMsg); UPD_DEFAULT_CHECK(PcdSccEnablePciMode); UPD_DEFAULT_CHECK(IgdRenderStandby); UPD_DEFAULT_CHECK(TxeUmaEnable); UPD_DEFAULT_CHECK(PcdOsSelection); UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled); UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); UPD_DEFAULT_CHECK(PcdEnableIgd); if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) || (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode; UpdData->PcdMrcInitTsegSize = smm_region_size() >> 20; printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); printk(FSP_INFO_LEVEL, "Aperture Size:\t\t%d MB\n", APERTURE_SIZE_BASE << UpdData->PcdApertureSize); printk(FSP_INFO_LEVEL, "IGD Memory Size:\t%d MB\n", UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); printk(FSP_INFO_LEVEL, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); /* Advance dev to PCI device 0.0 */ for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){ if (dev->path.type != DEVICE_PATH_PCI) continue; if (dev->path.pci.devfn == PCI_DEVFN(0x0,0)) break; } /* * Loop through all the SOC devices in the devicetree * enabling and disabling them as requested. */ for (; dev; dev = dev->sibling) { if (dev->path.type != DEVICE_PATH_PCI) continue; switch (dev->path.pci.devfn) { UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { /* Gold2 and earlier FSP: ISPEnable is the filed */ /* next to PcdGttSize in UPD_DATA_REGION struct */ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; printk (FSP_INFO_LEVEL, "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); } printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", UpdData->PcdEnableSdio?"Enabled":"Disabled"); break; case EMMC_DEV_FUNC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; case MMC45_DEV_FUNC: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; case XHCI_DEV_FUNC: UpdData->PcdEnableXhci = dev->enabled; break; case EHCI_DEV_FUNC: UpdData->PcdEnableXhci = !(dev->enabled); break; case LPE_DEV_FUNC: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else UpdData->PcdEnableLpe = 0; break; } } if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *)) printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n", acpi_pci_mode_strings[UpdData->PcdEnableLpe]); if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *)) printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s", emmc_mode_strings[UpdData->PcdeMMCBootMode]); if (UpdData->PcdEnableSata) printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n", UpdData->PcdSataMode?"AHCI":"IDE"); printk(FSP_INFO_LEVEL, "Xhci:\t\t\t%s\n", UpdData->PcdEnableXhci?"Enabled":"Disabled"); /* * set memory down parameters * Skip setting values if memory down is disabled * Skip setting values if FSP is earlier than gold 3 */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UPD_MEMDOWN_CHECK(EnableMemoryDown, DECREMENT_FOR_DEFAULT); if (UpdData->PcdMemoryParameters.EnableMemoryDown) { UPD_MEMDOWN_CHECK(DRAMSpeed, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DRAMType, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMM0Enable, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMM1Enable, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMDWidth, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMDensity, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMBusWidth, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMSides, DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtCL, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtRPtRCD, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtWR, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtWTR, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtRRD, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtRTP, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtFAW, NO_DECREMENT_FOR_DEFAULT); printk (FSP_INFO_LEVEL, "Memory Down Data Existed : %s\n"\ "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ "- Type (0: DDR3, 1: DDR3L) : %d\n"\ "- DIMM0 : %s\n"\ "- DIMM1 : %s\n"\ "- Width : x%d\n"\ "- Density : %dGbit\n" "- BudWidth : %dbit\n"\ "- Rank # : %d\n"\ "- tCL : %02X\n"\ "- tRPtRCD : %02X\n"\ "- tWR : %02X\n"\ "- tWTR : %02X\n"\ "- tRRD : %02X\n"\ "- tRTP : %02X\n"\ "- tFAW : %02X\n" , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" , UpdData->PcdMemoryParameters.DRAMSpeed , UpdData->PcdMemoryParameters.DRAMType , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) , (UpdData->PcdMemoryParameters.DIMMSides) + 1 , UpdData->PcdMemoryParameters.DIMMtCL , UpdData->PcdMemoryParameters.DIMMtRPtRCD , UpdData->PcdMemoryParameters.DIMMtWR , UpdData->PcdMemoryParameters.DIMMtWTR , UpdData->PcdMemoryParameters.DIMMtRRD , UpdData->PcdMemoryParameters.DIMMtRTP , UpdData->PcdMemoryParameters.DIMMtFAW ); } } }