void be_connect(void *data, int fd)
{
printf("connected %s %d\n", (char *)data, fd);
epdata_t *epd = NULL;
epd = smp_malloc(sizeof(epdata_t));
if(!epd) {
close(fd);
return;
}
epd->fd = fd;
epd->stime = now;
epd->se_ptr = se_add(loop_fd, fd, epd);
epd->timeout_ptr = add_timeout(epd, 1000, timeout_handle);
epd->out_buf = smp_malloc(1024);
epd->out_buf_len = sprintf(epd->out_buf,
"GET / HTTP/1.1\r\nUser-Agent: curl/7.24.0\r\nHost: www.163.com\r\nAccept: */*\r\n\r\n");
epd->out_buf_sended = 0;
se_be_read(epd->se_ptr, client_be_write);
client_be_write(epd->se_ptr);
}
static void be_accept(int client_fd, struct in_addr client_addr)
{
if(!set_nonblocking(client_fd, 1)) {
close(client_fd);
return;
}
epdata_t *epd = NULL;
epd = smp_malloc(sizeof(epdata_t));
if(!epd) {
close(client_fd);
return;
}
epd->fd = client_fd;
epd->client_addr = client_addr;
epd->stime = now;
epd->se_ptr = se_add(loop_fd, client_fd, epd);
epd->timeout_ptr = add_timeout(epd, 1000, timeout_handle);
se_be_read(epd->se_ptr, be_read);
}
void
cpuattach(struct device *parent, struct device *dev, void *aux)
{
struct cpu_info *ci;
int cpuno = dev->dv_unit;
int isr16k = 0;
int displayver;
if (cpuno == 0) {
ci = &cpu_info_primary;
#ifdef MULTIPROCESSOR
ci->ci_flags |= CPUF_RUNNING | CPUF_PRESENT | CPUF_PRIMARY;
cpuset_add(&cpus_running, ci);
#endif
}
#ifdef MULTIPROCESSOR
else {
ci = (struct cpu_info *)smp_malloc(sizeof(*ci));
if (ci == NULL)
panic("unable to allocate cpu_info\n");
bzero((char *)ci, sizeof(*ci));
ci->ci_next = cpu_info_list->ci_next;
cpu_info_list->ci_next = ci;
ci->ci_flags |= CPUF_PRESENT;
cpu_info[cpuno] = ci;
}
#endif
ci->ci_self = ci;
ci->ci_cpuid = cpuno;
ci->ci_dev = dev;
printf(": ");
displayver = 1;
switch (sys_config.cpu[cpuno].type) {
case MIPS_R4000:
if (CpuPrimaryInstCacheSize == 16384)
printf("MIPS R4400 CPU");
else
printf("MIPS R4000 CPU");
break;
case MIPS_R5000:
printf("MIPS R5000 CPU");
break;
case MIPS_R10000:
printf("MIPS R10000 CPU");
break;
case MIPS_R12000:
printf("MIPS R12000 CPU");
break;
case MIPS_R14000:
if (sys_config.cpu[cpuno].vers_maj > 2) {
sys_config.cpu[cpuno].vers_maj -= 2;
isr16k = 1;
}
printf("R1%d000 CPU", isr16k ? 6 : 4);
break;
case MIPS_R4200:
printf("NEC VR4200 CPU (ICE)");
break;
case MIPS_R4300:
printf("NEC VR4300 CPU");
break;
case MIPS_R4100:
printf("NEC VR41xx CPU");
break;
case MIPS_R4600:
printf("QED R4600 Orion CPU");
break;
case MIPS_R4700:
printf("QED R4700 Orion CPU");
break;
case MIPS_RM52X0:
printf("PMC-Sierra RM52X0 CPU");
break;
case MIPS_RM7000:
if (sys_config.cpu[cpuno].vers_maj < 2)
printf("PMC-Sierra RM7000 CPU");
else
printf("PMC-Sierra RM7000A CPU");
cpu_is_rm7k++;
break;
case MIPS_RM9000:
printf("PMC-Sierra RM9000 CPU");
break;
case MIPS_LOONGSON2:
printf("STC Loongson2%c CPU",
'C' + sys_config.cpu[cpuno].vers_min);
displayver = 0;
break;
default:
printf("Unknown CPU type (0x%x)",sys_config.cpu[cpuno].type);
break;
}
if (displayver != 0)
printf(" rev %d.%d", sys_config.cpu[cpuno].vers_maj,
sys_config.cpu[cpuno].vers_min);
printf(" %d MHz, ", sys_config.cpu[cpuno].clock / 1000000);
displayver = 1;
switch (sys_config.cpu[cpuno].fptype) {
case MIPS_SOFT:
printf("Software FP emulation");
break;
case MIPS_R4000:
printf("R4010 FPC");
break;
case MIPS_R10000:
printf("R10000 FPU");
break;
case MIPS_R12000:
printf("R12000 FPU");
break;
case MIPS_R14000:
printf("R1%d000 FPU", isr16k ? 6 : 4);
break;
case MIPS_R4200:
printf("VR4200 FPC (ICE)");
break;
case MIPS_R4600:
printf("R4600 Orion FPC");
break;
case MIPS_R4700:
printf("R4700 Orion FPC");
break;
case MIPS_R5000:
printf("R5000 based FPC");
break;
case MIPS_RM52X0:
printf("RM52X0 FPC");
break;
case MIPS_RM7000:
printf("RM7000 FPC");
break;
case MIPS_RM9000:
printf("RM9000 FPC");
break;
case MIPS_LOONGSON2:
printf("STC Loongson2%c FPU",
'C' + sys_config.cpu[cpuno].fpvers_min);
displayver = 0;
break;
default:
printf("Unknown FPU type (0x%x)", sys_config.cpu[cpuno].fptype);
break;
}
if (displayver != 0)
printf(" rev %d.%d", sys_config.cpu[cpuno].fpvers_maj,
sys_config.cpu[cpuno].fpvers_min);
printf("\n");
printf("cpu%d: cache L1-I %dKB", cpuno, CpuPrimaryInstCacheSize / 1024);
printf(" D %dKB ", CpuPrimaryDataCacheSize / 1024);
switch (CpuNWayCache) {
case 2:
printf("2 way");
break;
case 4:
printf("4 way");
break;
default:
printf("1 way");
break;
}
if (CpuSecondaryCacheSize != 0) {
switch (sys_config.cpu[cpuno].type) {
case MIPS_R10000:
case MIPS_R12000:
case MIPS_R14000:
printf(", L2 %dKB 2 way", CpuSecondaryCacheSize / 1024);
break;
case MIPS_RM7000:
case MIPS_RM9000:
case MIPS_LOONGSON2:
printf(", L2 %dKB 4 way", CpuSecondaryCacheSize / 1024);
break;
default:
printf(", L2 %dKB direct", CpuSecondaryCacheSize / 1024);
break;
}
}
if (CpuTertiaryCacheSize != 0)
printf(", L3 %dKB direct", CpuTertiaryCacheSize / 1024);
printf("\n");
#ifdef DEBUG
printf("cpu%d: Setsize %d:%d\n", cpuno,
CpuPrimaryInstSetSize, CpuPrimaryDataSetSize);
printf("cpu%d: Alias mask 0x%x\n", cpuno, CpuCacheAliasMask);
printf("cpu%d: Config Register %x\n", cpuno, CpuConfigRegister);
printf("cpu%d: Cache type %x\n", cpuno, CpuCacheType);
if (sys_config.cpu[cpuno].fptype == MIPS_RM7000) {
u_int tmp = CpuConfigRegister;
printf("cpu%d: ", cpuno);
printf("K0 = %1d ",0x7 & tmp);
printf("SE = %1d ",0x1 & (tmp>>3));
printf("DB = %1d ",0x1 & (tmp>>4));
printf("IB = %1d\n",0x1 & (tmp>>5));
printf("cpu%d: ", cpuno);
printf("DC = %1d ",0x7 & (tmp>>6));
printf("IC = %1d ",0x7 & (tmp>>9));
printf("TE = %1d ",0x1 & (tmp>>12));
printf("EB = %1d\n",0x1 & (tmp>>13));
printf("cpu%d: ", cpuno);
printf("EM = %1d ",0x1 & (tmp>>14));
printf("BE = %1d ",0x1 & (tmp>>15));
printf("TC = %1d ",0x1 & (tmp>>17));
printf("EW = %1d\n",0x3 & (tmp>>18));
printf("cpu%d: ", cpuno);
printf("TS = %1d ",0x3 & (tmp>>20));
printf("EP = %1d ",0xf & (tmp>>24));
printf("EC = %1d ",0x7 & (tmp>>28));
printf("SC = %1d\n",0x1 & (tmp>>31));
}
