static int adau1373_resume(struct snd_soc_codec *codec) { adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY); snd_soc_cache_sync(codec); return 0; }
static int aml_pmu4_audio_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) { codec->cache_only = false; codec->cache_sync = 1; snd_soc_cache_sync(codec); } break; case SND_SOC_BIAS_OFF: break; default: break; } codec->dapm.bias_level = level; return 0; }
static int ak4671_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct ak4671_platform_data *pdata = codec->dev->platform_data; int ret; switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { if (pdata && gpio_is_valid(pdata->gpio_npdn)) gpio_set_value(pdata->gpio_npdn, 1); mdelay(1); ret = snd_soc_cache_sync(codec); if (ret) { dev_err(codec->dev, "Failed to sync cache: %d\n", ret); return ret; } } snd_soc_update_bits(codec, AK4671_AD_DA_POWER_MANAGEMENT, AK4671_PMVCM, AK4671_PMVCM); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00); if (pdata && gpio_is_valid(pdata->gpio_npdn)) gpio_set_value(pdata->gpio_npdn, 0); codec->cache_sync = 1; break; } codec->dapm.bias_level = level; return 0; }
static int wm8971_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; switch (level) { case SND_SOC_BIAS_ON: /* set vmid to 50k and unmute dac */ snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x00c1); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) snd_soc_cache_sync(codec); /* mute dac and set vmid to 500k, enable VREF */ snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x0140); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, WM8971_PWR1, 0x0001); break; } codec->dapm.bias_level = level; return 0; }
static int wm8776_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { snd_soc_cache_sync(codec); /* Disable the global powerdown; DAPM does the rest */ snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0); } break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 1); break; } codec->dapm.bias_level = level; return 0; }
static int adav80x_resume(struct snd_soc_codec *codec) { adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); codec->cache_sync = 1; snd_soc_cache_sync(codec); return 0; }
static int ssm2602_resume(struct snd_soc_codec *codec) { snd_soc_cache_sync(codec); ssm2602_set_bias_level(codec, SND_SOC_BIAS_STANDBY); return 0; }
static int cs4271_soc_resume(struct snd_soc_codec *codec) { int ret; /* Restore codec state */ ret = snd_soc_cache_sync(codec); if (ret < 0) return ret; /* then disable the power-down bit */ ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); if (ret < 0) return ret; return 0; }
static int cs4271_soc_resume(struct snd_soc_codec *codec) { int ret; ret = snd_soc_cache_sync(codec); if (ret < 0) return ret; ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); if (ret < 0) return ret; return 0; }
static int sta32x_cache_sync(struct snd_soc_codec *codec) { unsigned int mute; int rc; if (!codec->cache_sync) return 0; /* mute during register sync */ mute = snd_soc_read(codec, STA32X_MMUTE); snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); sta32x_sync_coef_shadow(codec); rc = snd_soc_cache_sync(codec); snd_soc_write(codec, STA32X_MMUTE, mute); return rc; }
static int wm8940_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 val; u16 pwr_reg = snd_soc_read(codec, WM8940_POWER1) & 0x1F0; int ret = 0; switch (level) { case SND_SOC_BIAS_ON: pwr_reg |= (1 << 2) | (1 << 3); val = snd_soc_read(codec, WM8940_OUTPUTCTL); ret = snd_soc_write(codec, WM8940_OUTPUTCTL, val | 0x2); if (ret) break; ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1); break; case SND_SOC_BIAS_PREPARE: pwr_reg |= (1 << 2) | (1 << 3); ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = snd_soc_cache_sync(codec); if (ret < 0) { dev_err(codec->dev, "Failed to sync cache: %d\n", ret); return ret; } } pwr_reg |= (1 << 2) | (1 << 3); ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x2); break; case SND_SOC_BIAS_OFF: ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg); break; } codec->dapm.bias_level = level; return ret; }
static int wm8940_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 val; u16 pwr_reg = snd_soc_read(codec, WM8940_POWER1) & 0x1F0; int ret = 0; switch (level) { case SND_SOC_BIAS_ON: /* ensure bufioen and biasen */ pwr_reg |= (1 << 2) | (1 << 3); /* Enable thermal shutdown */ val = snd_soc_read(codec, WM8940_OUTPUTCTL); ret = snd_soc_write(codec, WM8940_OUTPUTCTL, val | 0x2); if (ret) break; /* set vmid to 75k */ ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1); break; case SND_SOC_BIAS_PREPARE: /* ensure bufioen and biasen */ pwr_reg |= (1 << 2) | (1 << 3); ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = snd_soc_cache_sync(codec); if (ret < 0) { dev_err(codec->dev, "Failed to sync cache: %d\n", ret); return ret; } } /* ensure bufioen and biasen */ pwr_reg |= (1 << 2) | (1 << 3); /* set vmid to 300k for standby */ ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x2); break; case SND_SOC_BIAS_OFF: ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg); break; } codec->dapm.bias_level = level; return ret; }
static int ak4641_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct ak4641_platform_data *pdata = codec->dev->platform_data; int ret; switch (level) { case SND_SOC_BIAS_ON: /* unmute */ snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0); break; case SND_SOC_BIAS_PREPARE: /* mute */ snd_soc_update_bits(codec, AK4641_DAC, 0x20, 0x20); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { if (pdata && gpio_is_valid(pdata->gpio_power)) gpio_set_value(pdata->gpio_power, 1); mdelay(1); if (pdata && gpio_is_valid(pdata->gpio_npdn)) gpio_set_value(pdata->gpio_npdn, 1); mdelay(1); ret = snd_soc_cache_sync(codec); if (ret) { dev_err(codec->dev, "Failed to sync cache: %d\n", ret); return ret; } } snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0x80); snd_soc_update_bits(codec, AK4641_PM2, 0x80, 0); break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, AK4641_PM1, 0x80, 0); if (pdata && gpio_is_valid(pdata->gpio_npdn)) gpio_set_value(pdata->gpio_npdn, 0); if (pdata && gpio_is_valid(pdata->gpio_power)) gpio_set_value(pdata->gpio_power, 0); codec->cache_sync = 1; break; } codec->dapm.bias_level = level; return 0; }
/* * The machine driver should call this from their set_bias_level; if there * isn't one then this can just be set as the set_bias_level function. */ static int wm9090_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 *reg_cache = codec->reg_cache; int i, ret; switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: snd_soc_update_bits(codec, WM9090_ANTIPOP2, WM9090_VMID_ENA, WM9090_VMID_ENA); snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1, WM9090_BIAS_ENA | WM9090_VMID_RES_MASK, WM9090_BIAS_ENA | 1 << WM9090_VMID_RES_SHIFT); msleep(1); /* Probably an overestimate */ break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Restore the register cache */ snd_soc_cache_sync(codec); } /* We keep VMID off during standby since the combination of * ground referenced outputs and class D speaker mean that * latency is not an issue. */ snd_soc_update_bits(codec, WM9090_POWER_MANAGEMENT_1, WM9090_BIAS_ENA | WM9090_VMID_RES_MASK, 0); snd_soc_update_bits(codec, WM9090_ANTIPOP2, WM9090_VMID_ENA, 0); break; case SND_SOC_BIAS_OFF: break; } codec->dapm.bias_level = level; return 0; }
static int max98504_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { int ret; msg_maxim("level=%d \n", level); switch (level) { case SND_SOC_BIAS_ON: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = snd_soc_cache_sync(codec); if (ret != 0) { dev_err(codec->dev, "Failed to sync cache: %d\n", ret); return ret; } } // snd_soc_update_bits(codec, MAX98504_REG_40_GLOBAL_ENABLE, // M98504_GLOBAL_EN_MASK, M98504_GLOBAL_EN_MASK); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: case SND_SOC_BIAS_OFF: //snd_soc_update_bits(codec, MAX98504_REG_40_GLOBAL_ENABLE, //M98504_GLOBAL_EN_MASK, 0x00); codec->cache_sync = 1; break; } codec->dapm.bias_level = level; return 0; }
static int cs4270_soc_resume(struct snd_soc_codec *codec) { struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); int reg; regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), cs4270->supplies); /* In case the device was put to hard reset during sleep, we need to * wait 500ns here before any I2C communication. */ ndelay(500); /* first restore the entire register cache ... */ snd_soc_cache_sync(codec); /* ... then disable the power-down bits */ reg = snd_soc_read(codec, CS4270_PWRCTL); reg &= ~CS4270_PWRCTL_PDN_ALL; return snd_soc_write(codec, CS4270_PWRCTL, reg); }
static int pmu3_resume(struct snd_soc_codec *codec) { //int i; //u16 *reg_cache = codec->reg_cache; //u16 *tmp_cache = kmemdup(reg_cache, sizeof(pmu3_reg_defaults), // GFP_KERNEL); snd_soc_cache_sync(codec); /* Bring the codec back up to standby first to minimise pop/clicks */ pmu3_set_bias_level(codec, SND_SOC_BIAS_STANDBY); /* Sync back everything else */ /*if (tmp_cache) { for (i = 2; i < ARRAY_SIZE(pmu3_reg_defaults); i++) if (tmp_cache[i] != reg_cache[i]) snd_soc_write(codec, i, tmp_cache[i]); kfree(tmp_cache); } else { dev_err(codec->dev, "Failed to allocate temporary cache\n"); }*/ return 0; }
/* liam need to make this lower power with dapm */ static int wm8974_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 power1 = snd_soc_read(codec, WM8974_POWER1) & ~0x3; switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: power1 |= 0x1; /* VMID 50k */ snd_soc_write(codec, WM8974_POWER1, power1); break; case SND_SOC_BIAS_STANDBY: power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN; if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { snd_soc_cache_sync(codec); /* Initial cap charge at VMID 5k */ snd_soc_write(codec, WM8974_POWER1, power1 | 0x3); mdelay(100); } power1 |= 0x2; /* VMID 500k */ snd_soc_write(codec, WM8974_POWER1, power1); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, WM8974_POWER1, 0); snd_soc_write(codec, WM8974_POWER2, 0); snd_soc_write(codec, WM8974_POWER3, 0); break; } codec->dapm.bias_level = level; return 0; }
static int wm8988_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1; switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: /* VREF, VMID=2x50k, digital enabled */ snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { snd_soc_cache_sync(codec); /* VREF, VMID=2x5k */ snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1); /* Charge caps */ msleep(100); } /* VREF, VMID=2*500k, digital stopped */ snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, WM8988_PWR1, 0x0000); break; } codec->dapm.bias_level = level; return 0; }
static int wm8741_resume(struct snd_soc_codec *codec) { snd_soc_cache_sync(codec); return 0; }
static int ak4535_resume(struct snd_soc_codec *codec) { snd_soc_cache_sync(codec); return 0; }
static int wm8737_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); int ret; switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: /* VMID at 2*75k */ snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, WM8737_VMIDSEL_MASK, 0); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); if (ret != 0) { dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); return ret; } snd_soc_cache_sync(codec); /* Fast VMID ramp at 2*2.5k */ snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, WM8737_VMIDSEL_MASK, 0x4); /* Bring VMID up */ snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT, WM8737_VMID_MASK | WM8737_VREF_MASK, WM8737_VMID_MASK | WM8737_VREF_MASK); msleep(500); } /* VMID at 2*300k */ snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL, WM8737_VMIDSEL_MASK, 2); break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT, WM8737_VMID_MASK | WM8737_VREF_MASK, 0); regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies); break; } codec->dapm.bias_level = level; return 0; }
static int wm8993_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); int ret; switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: /* VMID=2*40k */ snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, WM8993_VMID_SEL_MASK, 0x2); snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); if (ret != 0) return ret; snd_soc_cache_sync(codec); /* Tune DC servo configuration */ snd_soc_write(codec, 0x44, 3); snd_soc_write(codec, 0x56, 3); snd_soc_write(codec, 0x44, 0); /* Bring up VMID with fast soft start */ snd_soc_update_bits(codec, WM8993_ANTIPOP2, WM8993_STARTUP_BIAS_ENA | WM8993_VMID_BUF_ENA | WM8993_VMID_RAMP_MASK | WM8993_BIAS_SRC, WM8993_STARTUP_BIAS_ENA | WM8993_VMID_BUF_ENA | WM8993_VMID_RAMP_MASK | WM8993_BIAS_SRC); /* If either line output is single ended we * need the VMID buffer */ if (!wm8993->pdata.lineout1_diff || !wm8993->pdata.lineout2_diff) snd_soc_update_bits(codec, WM8993_ANTIPOP1, WM8993_LINEOUT_VMID_BUF_ENA, WM8993_LINEOUT_VMID_BUF_ENA); /* VMID=2*40k */ snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, WM8993_BIAS_ENA | 0x2); msleep(32); /* Switch to normal bias */ snd_soc_update_bits(codec, WM8993_ANTIPOP2, WM8993_BIAS_SRC | WM8993_STARTUP_BIAS_ENA, 0); } /* VMID=2*240k */ snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, WM8993_VMID_SEL_MASK, 0x4); snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, WM8993_TSHUT_ENA, 0); break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, WM8993_ANTIPOP1, WM8993_LINEOUT_VMID_BUF_ENA, 0); snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 0); snd_soc_update_bits(codec, WM8993_ANTIPOP2, WM8993_STARTUP_BIAS_ENA | WM8993_VMID_BUF_ENA | WM8993_VMID_RAMP_MASK | WM8993_BIAS_SRC, 0); #ifdef CONFIG_REGULATOR /* Post 2.6.34 we will be able to get a callback when * the regulators are disabled which we can use but * for now just assume that the power will be cut if * the regulator API is in use. */ codec->cache_sync = 1; #endif regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); break; } codec->dapm.bias_level = level; return 0; }