void init_done(void) {
// Configure sleep, and put the radio to sleep if no interfaces are active
wifi_fpm_set_sleep_type(MODEM_SLEEP_T);
if (wifi_get_opmode() == NULL_MODE) {
wifi_fpm_open();
wifi_fpm_do_sleep(0xfffffff);
}
#if MICROPY_REPL_EVENT_DRIVEN
uart_task_init();
#endif
mp_reset();
mp_hal_stdout_tx_str("\r\n");
#if MICROPY_REPL_EVENT_DRIVEN
pyexec_event_repl_init();
#endif
#if !MICROPY_REPL_EVENT_DRIVEN
soft_reset:
for (;;) {
if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) {
if (pyexec_raw_repl() != 0) {
break;
}
} else {
if (pyexec_friendly_repl() != 0) {
break;
}
}
}
soft_reset();
goto soft_reset;
#endif
}
static void check_diagnostics_mode(struct synaptics_drv_data *data)
{
/* Set report mode */
set_report_type(data, data->cmd_report_type);
switch (data->cmd_report_type) {
case REPORT_TYPE_RAW_CAP:
check_all_raw_cap(data);
break;
case REPORT_TYPE_TX_TO_TX:
check_tx_to_tx(data);
break;
case REPORT_TYPE_TX_TO_GND:
check_tx_to_gnd(data);
break;
case REPORT_TYPE_RX_TO_RX:
/* check the result */
check_rx_to_rx(data);
break;
#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301_KEYS)
case REPORT_TYPE_DELTA_CAP:
check_delta_cap(data);
break;
#endif
default:
break;
}
/* Reset */
soft_reset(data);
}
void init_done(void) {
#if MICROPY_REPL_EVENT_DRIVEN
uart_task_init();
#endif
mp_reset();
mp_hal_stdout_tx_str("\r\n");
#if MICROPY_REPL_EVENT_DRIVEN
pyexec_event_repl_init();
#endif
dupterm_task_init();
#if !MICROPY_REPL_EVENT_DRIVEN
soft_reset:
for (;;) {
if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) {
if (pyexec_raw_repl() != 0) {
break;
}
} else {
if (pyexec_friendly_repl() != 0) {
break;
}
}
}
soft_reset();
goto soft_reset;
#endif
}
int board_private_init(void)
{
unsigned int signature = 0;
act8600_output_set(1,0x1a); //core 1.2 -> 1.3
soft_reset();
/*add board privater gpio here ,it while be called by boot_main to nitialization*/
/*Check the recovery signature,if exist,skip the charge_detect func.*/
signature = cpm_get_scrpad();
if ((signature == RECOVERY_SIGNATURE) || (signature == RECOVERY_SIGNATURE_SEC)) {
if (signature == RECOVERY_SIGNATURE_SEC)
cpm_set_scrpad(0);
#if defined(CONFIG_XBOOT_LOW_BATTERY_DETECT)
goto skip_chgdet;
#endif
}
#if defined(CONFIG_XBOOT_LOW_BATTERY_DETECT)
/*Usb Cable detection ,If connected ,then do charge else skip it*/
//if(charge_detect()){
if(charge_detect()&&(low_battery_detect())){
charge_logo_display();
}
skip_chgdet:
/*Before Enter the system,check the battery status,
If low battery,then Enter the hibernate mode */
while(low_battery_detect() && !charge_detect()){
low_battery_warning();
jz_pm_do_hibernate();
}
#endif
}
// Runs from emulation thread
void handle_ui_keys() {
SDL_LockMutex(event_lock);
if (keys[SDL_SCANCODE_ESCAPE])
exit(0);
if (keys[SDL_SCANCODE_F3]) {
if (!cc_held) { corrupt_chance += 0x1000; printf("New corrupt chance is %u\n", corrupt_chance); }
cc_held = 1; }
else if (keys[SDL_SCANCODE_F4]) {
if (!cc_held) { corrupt_chance -= 0x1000; printf("New corrupt chance is %u\n", corrupt_chance); }
cc_held = 1; }
else cc_held = 0;
if (keys[SDL_SCANCODE_F5])
save_state();
else if (keys[SDL_SCANCODE_F8])
load_state();
handle_rewind(keys[SDL_SCANCODE_BACKSPACE]);
if (reset_pushed)
soft_reset();
SDL_UnlockMutex(event_lock);
}
int running_machine::run(bool firstrun)
{
int error = MAMERR_NONE;
/* move to the init phase */
m_current_phase = MACHINE_PHASE_INIT;
/* then finish setting up our local machine */
start();
/* load the configuration settings and NVRAM */
config_load_settings(this);
nvram_load(this);
sound_mute(this, FALSE);
/* display the startup screens */
ui_display_startup_screens(this, firstrun, !options_get_bool(&m_options, OPTION_SKIP_NAGSCREEN));
/* perform a soft reset -- this takes us to the running phase */
soft_reset();
/* run the CPUs until a reset or exit */
m_hard_reset_pending = false;
while ((!m_hard_reset_pending && !m_exit_pending) || m_saveload_schedule != SLS_NONE)
return 0;
return 0;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* This is needed to be able to call udelay(). It could be moved to
* memreset_setup, since udelay is called in memreset. */
init_timer();
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
}
/* The FSP returns here after the fsp_early_init call */
void ChipsetFspReturnPoint(EFI_STATUS Status,
VOID *HobListPtr)
{
*(void **)CBMEM_FSP_HOB_PTR=HobListPtr;
if (Status == 0xFFFFFFFF) {
soft_reset();
}
romstage_main_continue(Status, HobListPtr);
}
void sed1200_device::device_start()
{
memset(cgram, 0, sizeof(cgram));
memset(ddram, 0, sizeof(ddram));
if(memregion("cgrom"))
cgrom = memregion("cgrom")->base();
else
cgrom = nullptr;
soft_reset();
}
static bool cmd_settings_reset(Serial* pSer, char* value, size_t len) {
if(len > 0 && (value[0] == '1' || value[0] == '2' )) {
if(value[0] == '2') {
// clear the settings if AT+RESET=1
settings_clear();
SERIAL_PRINT_P(pSer,PSTR("Settings cleared, "));
}
SERIAL_PRINT_P(pSer,PSTR("Restarting...\r\n"));
//reboot the device
soft_reset();
}
return true;
}
ATADEV_TYPE DISK::detect_device_type()
{
soft_reset();
if (m_master) outportb(m_bus + ATA_REG_HDDEVSEL, 0xA0);
else outportb(m_bus + ATA_REG_HDDEVSEL, 0xB0);
io_wait();
unsigned char cl = inportb(m_bus + ATA_REG_LBA1); /* CYL_LO */
unsigned char ch = inportb(m_bus + ATA_REG_LBA2); /* CYL_HI */
printf("ATA device type %02X%02X\n",ch,cl);
/* differentiate ATA, ATAPI, SATA and SATAPI */
if (cl == 0x14 && ch == 0xEB) return ATADEV_PATAPI;
if (cl == 0x69 && ch == 0x96) return ATADEV_SATAPI;
if (cl == 0 && ch == 0) return ATADEV_PATA;
if (cl == 0x3c && ch == 0xc3) return ATADEV_SATA;
return ATADEV_UNKNOWN;
}
static int tlv320aic31_device_init(unsigned int num)
{
/* inite codec configs.*/
unsigned char temp = 0;
temp = tlv320aic31_read(IIC_device_addr[num], 0x2);
tlv320aic31_write(IIC_device_addr[0], 0x2, 0xaa);
if ( tlv320aic31_read(IIC_device_addr[num], 0x2) != 0xaa)
{
DPRINTK(0, "init aic31(%d) error", num);
return -1;
}
tlv320aic31_write(IIC_device_addr[num], 0x2, temp);
soft_reset(num);
/* reboot_notifier */
register_reboot_notifier(&tlv320aic31_reboot_notifier);
return 0;
}
static void cpsw_init_host_port(struct cpsw_priv *priv)
{
/* */
soft_reset("cpsw", &priv->regs->soft_reset);
cpsw_ale_start(priv->ale);
/* */
cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
/* */
__raw_writel(CPDMA_TX_PRIORITY_MAP,
&priv->host_port_regs->cpdma_tx_pri_map);
__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
cpsw_ale_control_set(priv->ale, priv->host_port,
ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1 << priv->host_port, 0, ALE_MCAST_FWD_2);
}
void SketchGardenNanode::HandleSketchGardenStatus(uint8_t status, uint16_t off, uint16_t len) {
char * ptr =(char*) (Ethernet::buffer + off);
char * last = (char*) (ptr + len);
char status_code[] = "xxx";
// if we scan the response for the first line that starts with '3' (i.e. '\r', '\n', '3', '\r', '\n')
// the next line will contain the 3-digit status code
while(ptr != last){
if( strncmp_P( ptr, PSTR("\r\n3\r\n"), 5 ) == 0 ){
// we know the next line contains the status code
strncpy(status_code, ptr + 5, 3);
if(strncmp_P(status_code, PSTR("300"), 3) == 0){
soft_reset();
}
break;
}
ptr++;
}
}
void sed1200_device::control_w(UINT8 data)
{
switch(data) {
case 0x04: case 0x05:
cursor_direction = data & 0x01;
break;
case 0x06: case 0x07:
cursor_step();
break;
case 0x08: case 0x09:
cursor_full = data & 0x01;
break;
case 0x0a: case 0x0b:
cursor_blinking = data & 0x01;
break;
case 0x0c: case 0x0d:
display_on = data & 0x01;
break;
case 0x0e: case 0x0f:
cursor_on = data & 0x01;
break;
case 0x10:
soft_reset();
break;
case 0x12: case 0x13:
break; // Number of lines selection
default:
if((data & 0xf0) == 0x20)
cgram_address = (data & 3)*8;
else if((data & 0xe0) == 0x40) {
cgram[cgram_address++] = data;
if(cgram_address == 4*8)
cgram_address = 0;
} else if(data & 0x80) {
cursor_address = data & 0x40 ? 10 : 0;
cursor_address += (data & 0x3f) >= 10 ? 9 : data & 0x3f;
}
break;
}
}
void HardFault_Handler()
{
u8 i = 5;
#ifdef OS_UCOS
OSIntEnter();
#endif
u_printf(ERR_FUN,"");
Telnet_Control("System well reset....%d",i);
while (1)
{
Sleep(1000);
Telnet_Control("\x8\x1b[\xff\x50%d",i);
}
Telnet_Control("\r\n");
soft_reset();
#ifdef OS_UCOS
OSIntExit();
#endif
}
static int tlv320aic31_device_init(unsigned int num)
{
#if 1
/* inite codec configs.*/
unsigned char temp = 0;
temp = tlv320aic31_read(IIC_device_addr[num],0x2);
tlv320aic31_write(IIC_device_addr[0],0x2,0xaa);
if( tlv320aic31_read(IIC_device_addr[num],0x2) != 0xaa)
{
DPRINTK(0,"init aic31(%d) error",num);
return -1;
}
tlv320aic31_write(IIC_device_addr[num],0x2,temp);
#endif
soft_reset(num);
#if 0
for (temp = 0;temp < 30;temp ++)
{
printk("0x%x, 0x%x\n",temp,tlv320aic31_read(IIC_device_addr[num],temp));
}
#endif
return 0;
}
static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
{
char name[32];
u32 slave_port;
sprintf(name, "slave-%d", slave->slave_num);
soft_reset(name, &slave->sliver->soft_reset);
/* */
__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
__raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map);
/* */
__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
cpsw_set_slave_mac(slave, priv);
slave->mac_control = 0; /* */
slave_port = cpsw_get_slave_port(priv, slave->slave_num);
cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1 << slave_port, 0, ALE_MCAST_FWD_2);
slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
&cpsw_adjust_link, 0, slave->data->phy_if);
if (IS_ERR(slave->phy)) {
dev_err(priv->dev, "phy %s not found on slave %d\n",
slave->data->phy_id, slave->slave_num);
slave->phy = NULL;
} else {
dev_info(priv->dev, "phy found : id is : 0x%x\n",
slave->phy->phy_id);
phy_start(slave->phy);
}
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb7xx_51xx_pci_port80();
}
post_code(0x30);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
post_code(0x32);
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_kill_watchdog(GPIO_DEV);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
update_microcode(val);
post_code(0x33);
cpuSetAMDMSR();
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
/* Setup any mainboard PCI settings etc. */
setup_mb_resource_map();
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode.
I think it could be done by putting the spinlock flag in the cache
of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
rs780_htinit();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x40);
// die("Die Before MCT init.");
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
struct sys_info *sysinfo = &sysinfo_car;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
enable_rs690_dev8();
sb600_lpc_init();
/* Pistachio used a FPGA to enable serial debug instead of a SIO
* and it doesn't require any special setup. */
console_init();
post_code(0x03);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
setup_pistachio_resource_map();
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
/* it will set up chains and store link pair for optimization later,
* it will init sblnk and sbbusn, nodes, sbdn */
ht_setup_chains_x(sysinfo);
/* run _early_setup before soft-reset. */
rs690_early_setup();
sb600_early_setup();
post_code(0x04);
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
post_code(0x05);
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
rs690_htinit();
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
post_code(0x06);
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x07);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_code(0x08);
rs690_before_pci_init();
sb600_before_pci_init();
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
#if 0
uint8_t tmp = 0;
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
pnp_set_logical_device(GPIO_DEV);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
#endif
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
0, 0, 0, 0,
// Node 1
DIMM1, DIMM3, 0, 0,
0, 0, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
print_info("now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
}
// FIXME why is this executed again? --->
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
// <--- FIXME why is this executed again?
print_info("now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
print_info("now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
init_timer();
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
print_debug("ht reset -\n");
soft_reset();
}
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
enable_fid_change();
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val;
msr_t msr;
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/*enable port80 decoding and southbridge poweron init */
sb_Poweron_Init();
}
post_code(0x30);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
post_code(0x32);
enable_rs780_dev8();
sb800_clk_output_48Mhz();
w83627hf_set_clksel_48(CLK_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
printk(BIOS_DEBUG, "\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
update_microcode(val);
post_code(0x33);
cpuSetAMDMSR(0);
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
/* Setup any mainboard PCI settings etc. */
setup_mb_resource_map();
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode.
I think it could be done by putting the spinlock flag in the cache
of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
/* run _early_setup before soft-reset. */
rs780_early_setup();
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
/* show final fid and vid */
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
rs780_htinit();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
rs780_before_pci_init();
post_code(0x42);
post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
post_code(0x43); /* Should never see this post code. */
}
//static int tlv320aic31_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
static long tlv320aic31_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned int __user *argp = (unsigned int __user *)arg;
unsigned int chip_num;
Audio_Ctrl temp;
Audio_Ctrl *audio_ctrl;
Codec_Datapath_Setup_Ctrl codec_datapath_setup_ctrl;
DAC_OUTPUT_SWIT_CTRL dac_output_swit_ctrl;
DAC_POWER_CTRL dac_power_ctrl;
In1_Adc_Ctrl in1_adc_ctrl ;
In2_Adc_Ctrl_Sample in2_adc_ctrl_sample ;
Adc_Pga_Dac_Gain_Ctrl adc_pga_dac_gain_ctrl;
Line_Hpcom_Out_Ctrl line_hpcom_out_ctrl;
Serial_Int_Ctrl serial_int_ctrl;
Serial_Data_Offset_Ctrl serial_data_offset_ctrl;
Ctrl_Mode ctrl_mode;
if(argp != NULL)
{
if(copy_from_user(&temp,argp,sizeof(Audio_Ctrl)))
{
return -EFAULT;
}
}
audio_ctrl = (Audio_Ctrl *)(&temp);
chip_num = audio_ctrl->chip_num;
switch(cmd)
{
case IN2LR_2_LEFT_ADC_CTRL:
in2_adc_ctrl_sample.b8 = tlv320aic31_read(IIC_device_addr[chip_num],17);
in2_adc_ctrl_sample.bit.in2l_adc_input_level_sample = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],17,in2_adc_ctrl_sample.b8);
break;
case IN2LR_2_RIGTH_ADC_CTRL:
in2_adc_ctrl_sample.b8 = tlv320aic31_read(IIC_device_addr[chip_num],18);
in2_adc_ctrl_sample.bit.in2r_adc_input_level_sample = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],18,in2_adc_ctrl_sample.b8);
break;
case IN1L_2_LEFT_ADC_CTRL:
in1_adc_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],19);
in1_adc_ctrl.bit.in1_adc_input_level = audio_ctrl->input_level;
in1_adc_ctrl.bit.adc_ch_power_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],19,in1_adc_ctrl.b8);
break;
case IN1R_2_RIGHT_ADC_CTRL:
in1_adc_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],22);
in1_adc_ctrl.bit.in1_adc_input_level = audio_ctrl->input_level;
in1_adc_ctrl.bit.adc_ch_power_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],22,in1_adc_ctrl.b8);
break;
case PGAL_2_HPLOUT_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],46);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],46,adc_pga_dac_gain_ctrl.b8);
break;
case DACL1_2_HPLOUT_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],47);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],47,adc_pga_dac_gain_ctrl.b8);
break;
case HPLOUT_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],51);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit. output_level = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],51,line_hpcom_out_ctrl.b8);
break;
case PGAL_2_HPLCOM_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],53);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],53,adc_pga_dac_gain_ctrl.b8);
break;
case DACL1_2_HPLCOM_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],54);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],54,adc_pga_dac_gain_ctrl.b8);
break;
case HPLCOM_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],58);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit.output_level = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],58,line_hpcom_out_ctrl.b8);
break;
case PGAR_2_HPROUT_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],63);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],63,adc_pga_dac_gain_ctrl.b8);
break;
case DACR1_2_HPROUT_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],64);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],64,adc_pga_dac_gain_ctrl.b8);
break;
case HPROUT_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],65);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit. output_level = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],65,line_hpcom_out_ctrl.b8);
break;
case PGAR_2_HPRCOM_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],70);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],70,adc_pga_dac_gain_ctrl.b8);
break;
case DACR1_2_HPRCOM_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],71);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],71,adc_pga_dac_gain_ctrl.b8);
break;
case HPRCOM_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],72);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit.output_level = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],72,line_hpcom_out_ctrl.b8);
break;
case PGAL_2_LEFT_LOP_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],81);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],81,adc_pga_dac_gain_ctrl.b8);
break;
case DACL1_2_LEFT_LOP_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],82);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],82,adc_pga_dac_gain_ctrl.b8);
break;
case LEFT_LOP_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],86);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit.output_level = audio_ctrl->input_level;
line_hpcom_out_ctrl.bit.power_status = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],86,line_hpcom_out_ctrl.b8);
break;
case PGAR_2_RIGHT_LOP_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],91);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],91,adc_pga_dac_gain_ctrl.b8);
break;
case DACR1_2_RIGHT_LOP_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],92);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],92,adc_pga_dac_gain_ctrl.b8);
break;
case RIGHT_LOP_OUTPUT_LEVEL_CTRL:
line_hpcom_out_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],93);
line_hpcom_out_ctrl.bit.if_mute = audio_ctrl->if_mute_route;
line_hpcom_out_ctrl.bit.output_level = audio_ctrl->input_level;
line_hpcom_out_ctrl.bit.power_status = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],93,line_hpcom_out_ctrl.b8);
break;
case SET_ADC_SAMPLE:
in2_adc_ctrl_sample.b8 = tlv320aic31_read(IIC_device_addr[chip_num],2);
in2_adc_ctrl_sample.bit.in2l_adc_input_level_sample = audio_ctrl->sample;
tlv320aic31_write(IIC_device_addr[chip_num],2,in2_adc_ctrl_sample.b8);
break;
case SET_DAC_SAMPLE:
in2_adc_ctrl_sample.b8 = tlv320aic31_read(IIC_device_addr[chip_num],2);
in2_adc_ctrl_sample.bit.in2r_adc_input_level_sample = audio_ctrl->sample;
tlv320aic31_write(IIC_device_addr[chip_num],2,in2_adc_ctrl_sample.b8);
//printk("set SET_DAC_SAMPLE,audio_ctrl->sample=%x\n",audio_ctrl->sample);
break;
case SET_DATA_LENGTH:
serial_int_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],9);;
serial_int_ctrl.bit.data_length = audio_ctrl->data_length;
//tlv320aic31_write(IIC_device_addr[chip_num],9,serial_int_ctrl.b8);
break;
case SET_TRANSFER_MODE:
serial_int_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],9);
serial_int_ctrl.bit.transfer_mode = audio_ctrl->trans_mode;
tlv320aic31_write(IIC_device_addr[chip_num],9,serial_int_ctrl.b8);
break;
case SET_CTRL_MODE:
//tlv320aic31_write(IIC_device_addr[chip_num],0x1,0x80);
//udelay(50);
ctrl_mode.b8 = tlv320aic31_read(IIC_device_addr[chip_num],8);
ctrl_mode.bit.bit_clock_dic_ctrl = audio_ctrl->ctrl_mode;
ctrl_mode.bit.work_clock_dic_ctrl = audio_ctrl->ctrl_mode;
ctrl_mode.bit.bit_work_dri_ctrl = audio_ctrl->ctrl_mode;
tlv320aic31_write(IIC_device_addr[chip_num],8,ctrl_mode.b8);
#if 0
/* 设置时钟 */
if (1 == audio_ctrl->ctrl_mode
|| (AC31_SET_48K_SAMPLERATE != audio_ctrl->sample && AC31_SET_44_1K_SAMPLERATE != audio_ctrl->sample))
{
/* aic31作主模式或者采样率不为44.1K/48KHZ的情况下，使用外部的12.288MHZ的晶振作为MCLK输入并产生内部工作主时钟 */
if ((1 == audio_ctrl->if_44100hz_series))
{
/* 如果为44.1KHZ系列的采样样 */
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,0x1c); /* J=7 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x36); /* reg 5 and 6 set D=3500*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0xb0);
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.b8 |= 0x80; /* FSref = 44.1 kHz */
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],11,0x1); /* R=1 */
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],102,0xc2);
}
else
{
/* 如果为非44.1KHZ系列的采样样 */
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,0x20); /* J=8 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x0); /* reg 5 and 6 set D=0000*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0x0);
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.b8 &= 0x7f; /* FSref = 48 kHz */
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],11,0x1); /* R=1 */
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],102,0xc2);
}
}
else
{
/* aic31做从模式且采样率为44.1K/48KHZ的情况下，由BCLK产生内部工作主时钟 */
tlv320aic31_write(IIC_device_addr[chip_num],102,0x22); /* uses PLLCLK and BCLK */
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
if ((1 == audio_ctrl->if_44100hz_series))
{
codec_datapath_setup_ctrl.b8 |= 0x80; /* FSref = 44.1 kHz */
}
else
{
codec_datapath_setup_ctrl.b8 &= 0x7f; /* FSref = 48 kHz */
}
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,32<<2); /* set PLL J to 32 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x0); /* reg 5 and 6 set D=0000*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0); /* CODEC_CLKIN uses PLLDIV_OUT */
tlv320aic31_write(IIC_device_addr[chip_num],11,0x2); /* R = 2 */
}
#else
/* 设置时钟 */
/* aic31,由aiao提供mclk */
switch(audio_ctrl->sampleRate)
{
case 8000:
case 16000:
case 32000:
{
/* 如果为32KHZ系列的采样样 */
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,0x30); /* J=12 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x0); /* reg 5 and 6 set D=0000*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0x0);
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.b8 &= 0x7f; /* FSref = 48 kHz */
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],11,0x1); /* R=1 */
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],102,0xc2);
}
break;
case 12000:
case 24000:
case 48000:
{
/* 如果为48KHZ系列的采样样 */
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,0x20); /* J=8 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x0); /* reg 5 and 6 set D=0000*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0x0);
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.b8 &= 0x7f; /* FSref = 48 kHz */
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],11,0x1); /* R=1 */
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],102,0xc2);
}
break;
case 11025:
case 22050:
case 44100:
{
/* 如果为44.1KHZ系列的采样样 */
tlv320aic31_write(IIC_device_addr[chip_num],3,0x81); /* P=1 */
tlv320aic31_write(IIC_device_addr[chip_num],4,0x20); /* J=7 */
tlv320aic31_write(IIC_device_addr[chip_num],5,0x00); /* reg 5 and 6 set D=0000*/
tlv320aic31_write(IIC_device_addr[chip_num],6,0x00);
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.b8 |= 0x80; /* FSref = 44.1 kHz */
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
tlv320aic31_write(IIC_device_addr[chip_num],11,0x1); /* R=1 */
tlv320aic31_write(IIC_device_addr[chip_num],101,0x0);
tlv320aic31_write(IIC_device_addr[chip_num],102,0xc2);
}
break;
default:
printk("aic31 unsupport sampleRate %d\n", audio_ctrl->sampleRate);
return -1;
}
#endif
break;
case LEFT_DAC_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],43);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],43,adc_pga_dac_gain_ctrl.b8);
break;
case RIGHT_DAC_VOL_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],44);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],44,adc_pga_dac_gain_ctrl.b8);
break;
case LEFT_DAC_POWER_SETUP:
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.bit.left_dac_datapath_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
dac_power_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],37);
dac_power_ctrl.bit.left_dac_power_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],37,dac_power_ctrl.b8);
break;
case RIGHT_DAC_POWER_SETUP:
codec_datapath_setup_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],7);
codec_datapath_setup_ctrl.bit.right_dac_datapath_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],7,codec_datapath_setup_ctrl.b8);
dac_power_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],37);
dac_power_ctrl.bit.right_dac_power_ctrl = audio_ctrl->if_powerup;
tlv320aic31_write(IIC_device_addr[chip_num],37,dac_power_ctrl.b8);
break;
case DAC_OUT_SWITCH_CTRL:
dac_output_swit_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],41);
dac_output_swit_ctrl.bit.left_dac_swi_ctrl = audio_ctrl->dac_path;
dac_output_swit_ctrl.bit.right_dac_swi_ctrl = audio_ctrl->dac_path;
tlv320aic31_write(IIC_device_addr[chip_num],41,dac_output_swit_ctrl.b8);
break;
case LEFT_ADC_PGA_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],15);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],15,adc_pga_dac_gain_ctrl.b8);
break;
case RIGHT_ADC_PGA_CTRL:
adc_pga_dac_gain_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],16);
adc_pga_dac_gain_ctrl.bit.if_mute_route = audio_ctrl->if_mute_route;
adc_pga_dac_gain_ctrl.bit.input_vol_level_ctrl = audio_ctrl->input_level;
tlv320aic31_write(IIC_device_addr[chip_num],16,adc_pga_dac_gain_ctrl.b8);
break;
case SET_SERIAL_DATA_OFFSET:
serial_data_offset_ctrl.b8 = tlv320aic31_read(IIC_device_addr[chip_num],10);
serial_data_offset_ctrl.bit.serial_data_offset = audio_ctrl->data_offset;
tlv320aic31_write(IIC_device_addr[chip_num],10,serial_data_offset_ctrl.b8);
break;
case SOFT_RESET:
//printk("[Func]:%s [Line]:%d [Info]:%s\n", __FUNCTION__, __LINE__, "invalid attribute");
soft_reset(chip_num);
break;
case TLV320AIC31_REG_DUMP:
tlv320aic31_reg_dump(102);
break;
default:
break;
}
return 0;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr [] = {
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
int needs_reset;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
sio_gpio_setup();
setup_mb_resource_map();
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
//bx_a010- wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
#if 1
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
#endif
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
#if 0
int i;
for(i=0;i<2;i++) {
activate_spd_rom(sysinfo->ctrl+i);
dump_smbus_registers();
}
#endif
#if 0
int i;
for(i=1;i<256;i<<=1) {
change_i2c_mux(i);
dump_smbus_registers();
}
#endif
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0
print_pci_devices();
#endif
#if 0
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
post_cache_as_ram();
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_khepri_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}
int running_machine::run(bool firstrun)
{
int error = MAMERR_NONE;
// use try/catch for deep error recovery
try
{
// move to the init phase
m_current_phase = MACHINE_PHASE_INIT;
// if we have a logfile, set up the callback
if (options().log())
{
m_logfile = auto_alloc(*this, emu_file(OPEN_FLAG_WRITE | OPEN_FLAG_CREATE | OPEN_FLAG_CREATE_PATHS));
file_error filerr = m_logfile->open("error.log");
assert_always(filerr == FILERR_NONE, "unable to open log file");
add_logerror_callback(logfile_callback);
}
// then finish setting up our local machine
start();
// load the configuration settings and NVRAM
bool settingsloaded = config_load_settings(*this);
nvram_load(*this);
sound().ui_mute(false);
// display the startup screens
ui_display_startup_screens(*this, firstrun, !settingsloaded);
// perform a soft reset -- this takes us to the running phase
soft_reset();
// run the CPUs until a reset or exit
m_hard_reset_pending = false;
while ((!m_hard_reset_pending && !m_exit_pending) || m_saveload_schedule != SLS_NONE)
{
g_profiler.start(PROFILER_EXTRA);
// execute CPUs if not paused
if (!m_paused)
m_scheduler.timeslice();
// otherwise, just pump video updates through
else
m_video->frame_update();
// handle save/load
if (m_saveload_schedule != SLS_NONE)
handle_saveload();
g_profiler.stop();
}
// and out via the exit phase
m_current_phase = MACHINE_PHASE_EXIT;
// save the NVRAM and configuration
sound().ui_mute(true);
nvram_save(*this);
config_save_settings(*this);
}
catch (emu_fatalerror &fatal)
{
mame_printf_error("%s\n", fatal.string());
error = MAMERR_FATALERROR;
if (fatal.exitcode() != 0)
error = fatal.exitcode();
}
catch (emu_exception &)
{
mame_printf_error("Caught unhandled emulator exception\n");
error = MAMERR_FATALERROR;
}
catch (std::bad_alloc &)
{
mame_printf_error("Out of memory!\n");
error = MAMERR_FATALERROR;
}
// call all exit callbacks registered
call_notifiers(MACHINE_NOTIFY_EXIT);
zip_file_cache_clear();
// close the logfile
auto_free(*this, m_logfile);
return error;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
}
post_code(0x30);
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
post_code(0x32);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
update_microcode(val);
post_code(0x33);
cpuSetAMDMSR();
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
/* Setup any mainboard PCI settings etc. */
setup_mb_resource_map();
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
* It would be nice to fixup prink spinlocks for ROM XIP mode.
* I think it could be done by putting the spinlock flag in the cache
* of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
wants_reset = mcp55_early_setup_x();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
if (wants_reset)
printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x3D);
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
uart_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if SET_FIDVID == 1
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
