void
sonic_jazzio_attach(device_t parent, device_t self, void *aux)
{
struct sonic_softc *sc = device_private(self);
struct jazzio_attach_args *ja = aux;
int i;
uint8_t enaddr[ETHER_ADDR_LEN];
sc->sc_dev = self;
sc->sc_st = ja->ja_bust;
sc->sc_dmat = ja->ja_dmat;
aprint_normal(": SONIC Ethernet\n");
/* Map the device. */
if (bus_space_map(sc->sc_st, ja->ja_addr, SONIC_NREGS * 4,
0, &sc->sc_sh) != 0) {
aprint_error_dev(sc->sc_dev, "unable to map SONIC registers\n");
return;
}
/* We run in 32-bit mode. */
sc->sc_32bit = 1;
/* BMODE is set for little-endian. */
sc->sc_bigendian = 0;
/* Regs are 16-bit, plus 16-bit pad. */
for (i = 0; i < SONIC_NREGS; i++)
sc->sc_regmap[i] = i * 4;
/*
* Configure DCR:
*
* - Latched bug retry
* - Synchronous bus (memory cycle 2 clocks)
* - 0 wait states added (WC0,WC1 == 0,0)
* - 4 byte Rx DMA threshold (RFT0,RFT1 == 0,0)
* - 28 byte Tx DMA threshold (TFT0,TFT1 == 1,1)
* XXX There was a comment
* "XXX RFT & TFT according to MIPS manual"
* in old MD sys/arch/arc/dev/if_sn.c in Attic.
*/
sc->sc_dcr = DCR_LBR | DCR_SBUS | DCR_TFT0 | DCR_TFT1;
sc->sc_dcr2 = 0;
/* Hook up our interrupt handler. */
jazzio_intr_establish(ja->ja_intr, sonic_intr, sc);
/* The Ethernet address is from the product ID. */
memcpy(enaddr, arc_product_id, sizeof(enaddr));
/* Finish off the attach. */
sonic_attach(sc, enaddr);
}
void
sonic_jazzio_attach(struct device *parent, struct device *self, void *aux)
{
struct sonic_softc *sc = (void *) self;
struct jazzio_attach_args *ja = aux;
int i;
uint8_t enaddr[ETHER_ADDR_LEN];
sc->sc_st = ja->ja_bust;
sc->sc_dmat = ja->ja_dmat;
printf(": SONIC Ethernet\n");
/* Map the device. */
if (bus_space_map(sc->sc_st, ja->ja_addr, SONIC_NREGS * 4,
0, &sc->sc_sh) != 0) {
printf("%s: unable to map SONIC registers\n",
sc->sc_dev.dv_xname);
return;
}
/* We run in 32-bit mode. */
sc->sc_32bit = 1;
/* BMODE is set for little-endian. */
sc->sc_bigendian = 0;
/* Regs are 16-bit, plus 16-bit pad. */
for (i = 0; i < SONIC_NREGS; i++)
sc->sc_regmap[i] = i * 4;
/*
* Configure DCR:
*
* - Latched bug retry
* - Synchronous bus (memory cycle 2 clocks)
* - 0 wait states added (WC0,WC1 == 0,0)
*/
sc->sc_dcr = DCR_LBR | DCR_SBUS;
sc->sc_dcr2 = 0;
/* Hook up our interrupt handler. */
jazzio_intr_establish(ja->ja_intr, sonic_intr, sc);
/* The Ethernet address is from the product ID. */
memcpy(enaddr, arc_product_id, sizeof(enaddr));
/* Finish off the attach. */
sonic_attach(sc, enaddr);
}