static void sossi_start_transfer(void) { /* WE */ sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4); /* CS active low */ sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30); }
static void set_cycles(unsigned int len) { unsigned long nr_cycles = len / (sossi.bus_pick_width / 8); BUG_ON((nr_cycles - 1) & ~0x3ffff); sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff); sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff); }
static void sossi_write_command(const void *data, unsigned int len) { set_timing(WR_ACCESS); /* CMD#/DATA */ sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18); set_cycles(len); sossi_start_transfer(); send_data(data, len); sossi_stop_transfer(); wait_end_of_write(); }
static void sossi_write_command(const void *data, unsigned int len) { clk_enable(sossi.fck); set_timing(WR_ACCESS); _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width); /* CMD#/DATA */ sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18); set_cycles(len); sossi_start_transfer(); send_data(data, len); sossi_stop_transfer(); wait_end_of_write(); clk_disable(sossi.fck); }
static void _set_tearsync_mode(int mode, unsigned line) { u32 l; l = sossi_read_reg(SOSSI_TEARING_REG); l &= ~(((1 << 11) - 1) << 15); l |= line << 15; l &= ~(0x3 << 26); l |= mode << 26; sossi_write_reg(SOSSI_TEARING_REG, l); if (mode) sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */ else sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6); }