static void __dead2 hikey_system_off(void)
{
NOTICE("%s: off system\n", __func__);
/* Pull down GPIO_0_0 to trigger PMIC shutdown */
mmio_write_32(0xF8001810, 0x2); /* Pinmux */
mmio_write_8(0xF8011400, 1); /* Pin direction */
mmio_write_8(0xF8011004, 0); /* Pin output value */
/* Wait for 2s to power off system by PMIC */
sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
mdelay(2000);
/*
* PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low,
* and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2
* through Jumper 1-2. So, to complete shutdown, user needs to manually
* remove Jumper 1-2.
*/
NOTICE("+------------------------------------------+\n");
NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n");
NOTICE("| DANGER: SoC is still burning. DANGER! |\n");
NOTICE("| Board will be reboot to avoid overheat |\n");
NOTICE("+------------------------------------------+\n");
/* Send the system reset request */
mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
wfi();
panic();
}
int __init arch_cpu_clockevent_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(V2M_SYSCTL, 0x1000);
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
val = vmm_readl((void *)sctl_base) | SCCTRL_TIMEREN0SEL_TIMCLK;
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Map timer registers */
ca15x4_timer0_base = vmm_host_iomap(V2M_TIMER0, 0x1000);
/* Initialize timers */
rc = sp804_timer_init(ca15x4_timer0_base,
IRQ_V2M_TIMER0,
ca15x4_timer0_handler);
if (rc) {
return rc;
}
return VMM_OK;
}
void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
#ifdef FVP_VE_USE_SP804_TIMER
/*
* Enable the clock override for SP804 timer 0, which means that no
* clock dividers are applied and the raw (35 MHz) clock will be used
*/
mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
/* Initialize delay timer driver using SP804 dual timer 0 */
sp804_timer_init(V2M_SP804_TIMER0_BASE,
SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
#else
generic_delay_timer_init();
#endif /* FVP_VE_USE_SP804_TIMER */
}
int __init arch_cpu_clocksource_init(void)
{
int rc;
u32 val;
virtual_addr_t sctl_base;
/* Map control registers */
sctl_base = vmm_host_iomap(V2M_SYSCTL, 0x1000);
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
val = vmm_readl((void *)sctl_base) | SCCTRL_TIMEREN1SEL_TIMCLK;
vmm_writel(val, (void *)sctl_base);
/* Unmap control register */
rc = vmm_host_iounmap(sctl_base, 0x1000);
if (rc) {
return rc;
}
/* Map timer registers */
ca15x4_timer1_base = vmm_host_iomap(V2M_TIMER1, 0x1000);
/* Initialize timers */
rc = sp804_timer_init(ca15x4_timer1_base, IRQ_V2M_TIMER1, NULL);
if (rc) {
return rc;
}
/* Configure timer1 as free running source */
rc = sp804_timer_counter_start(ca15x4_timer1_base);
if (rc) {
return rc;
}
sp804_timer_enable(ca15x4_timer1_base);
return VMM_OK;
}
