Example #1
0
long int
initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_DDR_DLL)
	{
		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
		uint temp_ddrdll = 0;

		/* Work around to stabilize DDR DLL */
		temp_ddrdll = gur->ddrdllcr;
		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
		asm("sync;isync;msync");
	}
#endif

	dram_size = spd_sdram ();

#if defined(CONFIG_DDR_ECC)
	/* Initialize and enable DDR ECC.
	*/
	ddr_enable_ecc(dram_size);
#endif

	return dram_size;
}
Example #2
0
long int initdram (int board_type)
{
    long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
    dram_size = spd_sdram ();
#else
    dram_size = fixed_sdram ();
#endif

#if defined(CFG_RAMBOOT)
    puts ("    DDR: ");
    return dram_size;
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
    /*
     * Initialize and enable DDR ECC.
     */
    ddr_enable_ecc (dram_size);
#endif

    puts ("    DDR: ");
    return dram_size;
}
Example #3
0
/* -------------------------------------------------------------------------
  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  the necessary info for SDRAM controller configuration
   ------------------------------------------------------------------------- */
long int initdram(int board_type)
{
	long int ret;

	ret = spd_sdram();
	return ret;
}
long int initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CFG_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}
Example #5
0
/* -------------------------------------------------------------------------
  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  the necessary info for SDRAM controller configuration
   ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
#if 0
	return  spd_sdram (0);
#else
	return 0x01000000;	// We ware already initilized sdram.
#endif
}
Example #6
0
long int initdram (int board_type)
{
	long dram_size = 0;

	set_leds(1);			/* display boot info counter */
	dram_size = spd_sdram();
	set_leds(2);			/* display boot info counter */

	return dram_size;
}
phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif
	return dram_size;
}
Example #8
0
phys_size_t initdram(int board_type)
{
    u32 msize;

    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
    volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;

    /* Enable PCI_CLK[0:1] */
    clk->occr |= 0xc0000000;
    udelay(2000);

#if defined(CONFIG_SPD_EEPROM)
    msize = spd_sdram();
#else
    immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
    u32 msize_log2;

    msize = CONFIG_SYS_DDR_SIZE;
    msize_log2 = __ilog2(msize);

    im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
    im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);

    im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
    udelay(50000);

    im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
    udelay(1000);

    im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
    im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
    udelay(1000);

    im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
    im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
    im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
    im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
    im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
    im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
    im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
    im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
    im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    __asm__ __volatile__("sync");
    udelay(1000);

    im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
    udelay(2000);
#endif
    setup_serdes();

    return msize << 20;
}
Example #9
0
long int
initdram(int board_type)
{
	long dram_size = 0;
	extern long spd_sdram (void);
	volatile immap_t *immap = (immap_t *)CFG_IMMR;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur= &immap->im_gur;
	    int i,x;

	    x = 10;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    gur->ddrdllcr = 0x81000000;
	    asm("sync;isync;msync");
	    udelay (200);
	    while (gur->ddrdllcr != 0x81000100)
	    {
	    	gur->devdisr = gur->devdisr | 0x00010000;
		asm("sync;isync;msync");
		for (i=0; i<x; i++)
		    ;
		gur->devdisr = gur->devdisr & 0xfff7ffff;
		asm("sync;isync;msync");
		x++;
	    }
	}
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_DDR_ECC)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	puts("    DDR: ");
	return dram_size;
}
Example #10
0
long int
initdram(int board_type)
{
	long dram_size = 0;
	extern long spd_sdram (void);
	volatile immap_t *immap = (immap_t *)CFG_IMMR;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur= &immap->im_gur;
	    uint temp_ddrdll = 0;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    temp_ddrdll = gur->ddrdllcr;
	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	    asm("sync;isync;msync");
	}
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	/*
	 * Initialize SDRAM.
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}
Example #11
0
long int initdram(int board_type)
{
	immap_t *im = (immap_t *) CFG_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus DDR size(bytes) */
	return (msize * 1024 * 1024);
}
long int
initdram(int board_type)
{
	long dram_size = 0;
	volatile immap_t *immap = (immap_t *)CFG_IMMR;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur= &immap->im_gur;

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
	dram_size = spd_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}
Example #13
0
int dram_init(void)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -ENXIO;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus DDR size(bytes) */
	gd->ram_size = msize * 1024 * 1024;

	return 0;
}
long int initdram (int board_type)
{
    long dram_size = 0;

#if !defined(CONFIG_RAM_AS_FLASH)
    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
    sys_info_t sysinfo;
    uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif

#if defined(CONFIG_DDR_DLL)
    uint temp_ddrdll = 0;

    /* Work around to stabilize DDR DLL */
    temp_ddrdll = gur->ddrdllcr;
    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
    asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
    dram_size = spd_sdram ();
#else
    dram_size = fixed_sdram ();
#endif

#if defined(CFG_RAMBOOT)
    return dram_size;
#endif

#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
    get_sys_info(&sysinfo);
    /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
    if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
        lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
    } else {
        lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
        udelay(200);
        temp_lbcdll = gur->lbcdllcr;
        gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
        asm("sync;isync;msync");
    }
    lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
    lbc->br2 = CFG_BR2_PRELIM;
    lbc->lbcr = CFG_LBC_LBCR;
    lbc->lsdmr = CFG_LBC_LSDMR_1;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_2;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_3;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_4;
    asm("sync");
    * (ulong *)0 = 0x000000ff;
    lbc->lsdmr = CFG_LBC_LSDMR_5;
    asm("sync");
    lbc->lsrt = CFG_LBC_LSRT;
    asm("sync");
    lbc->mrtpr = CFG_LBC_MRTPR;
    asm("sync");
#endif

#if defined(CONFIG_DDR_ECC)
    {
        /* Initialize all of memory for ECC, then
         * enable errors */
        uint *p = 0;
        uint i = 0;
        volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
        dma_init();
        for (*p = 0; p < (uint *)(8 * 1024); p++) {
            if (((unsigned int)p & 0x1f) == 0) {
                dcbz(p);
            }
            *p = (unsigned int)0xdeadbeef;
            if (((unsigned int)p & 0x1c) == 0x1c) {
                dcbf(p);
            }
        }

        /* 8K */
        dma_xfer((uint *)0x2000,0x2000,(uint *)0);
        /* 16K */
        dma_xfer((uint *)0x4000,0x4000,(uint *)0);
        /* 32K */
        dma_xfer((uint *)0x8000,0x8000,(uint *)0);
        /* 64K */
        dma_xfer((uint *)0x10000,0x10000,(uint *)0);
        /* 128k */
        dma_xfer((uint *)0x20000,0x20000,(uint *)0);
        /* 256k */
        dma_xfer((uint *)0x40000,0x40000,(uint *)0);
        /* 512k */
        dma_xfer((uint *)0x80000,0x80000,(uint *)0);
        /* 1M */
        dma_xfer((uint *)0x100000,0x100000,(uint *)0);
        /* 2M */
        dma_xfer((uint *)0x200000,0x200000,(uint *)0);
        /* 4M */
        dma_xfer((uint *)0x400000,0x400000,(uint *)0);

        for (i = 1; i < dram_size / 0x800000; i++) {
            dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
        }

        /* Enable errors for ECC */
        ddr->err_disable = 0x00000000;
        asm("sync;isync;msync");
    }
#endif

    return dram_size;
}
Example #15
0
long int initdram (int board_type)
{
	return  spd_sdram (0);
}
Example #16
0
phys_size_t initdram(int board_type)
{
	return spd_sdram();
}
Example #17
0
/*
 * dram_init() reads EEPROM via I2c. EEPROM contains all of
 * the necessary info for SDRAM controller configuration
 */
int dram_init(void)
{
	gd->ram_size = spd_sdram();

	return 0;
}