/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
spi_enable_clock(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register.
spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR).
spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device.
spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);
/* Set communication parameters for CS0 */
spi_chip_sel = 0;
spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed.
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS1 */
spi_chip_sel = 1;
spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz.
spi_clk_pol = 0;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS2 */
spi_chip_sel = 2;
spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Enable SPI Communication */
spi_enable(SPI_MASTER_BASE);
}
/**
* \internal
* \brief Initialize Proxy PLC controller.
*
* This function will change the system clock prescaler configuration to
* match the parameters.
*
* \note The parameters to this function are device-specific.
*
*/
static void _pplc_if_config(void)
{
uint32_t ul_cpuhz;
uint8_t uc_div;
ul_cpuhz = sysclk_get_cpu_hz();
uc_div = ul_cpuhz / gs_ul_pplc_clock;
/* Enable SPI peripheral. */
spi_enable_clock(PPLC_SPI_MODULE);
/* Reset SPI */
spi_disable(PPLC_SPI_MODULE);
spi_reset(PPLC_SPI_MODULE);
/* Configure SPI */
spi_set_master_mode(PPLC_SPI_MODULE);
spi_disable_mode_fault_detect(PPLC_SPI_MODULE);
spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS);
spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0);
spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1);
spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT);
spi_set_fixed_peripheral_select(PPLC_SPI_MODULE);
spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div);
spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS,
PPLC_DLYBCT);
spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX);
/* Get board PPLC PDC base address and enable receiver and transmitter */
g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE);
spi_enable(PPLC_SPI_MODULE);
}
spi_p spi_new_instance(Spi * spi_base, uint8_t spi_chip_sel, uint32_t spi_freq, uint8_t spi_mode, uint8_t buffer_size, void(*handler_call_back )(spi_p, uint8_t))
{
_spi_base = spi_base;
if (!spi_is_enabled(_spi_base)) {
_spi_init_base(spi_base);
}
spi_p _spi = malloc(sizeof *_spi);
_spi->_call_back = handler_call_back;
_spi->_cs_pin = spi_chip_sel;
_spi->_spi_rx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
_spi->_spi_tx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
union spi_buffer_element *spi_tx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
union spi_buffer_element *spi_rx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
fifo_init(_spi->_spi_rx_fifo_desc, spi_rx_fifo_buffer, buffer_size);
fifo_init(_spi->_spi_tx_fifo_desc, spi_tx_fifo_buffer, buffer_size);
spi_set_peripheral_chip_select_value(spi_base, spi_get_pcs(spi_chip_sel));
switch (spi_mode)
{
case 0:
spi_set_clock_polarity(spi_base, spi_chip_sel,0);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 1:
spi_set_clock_polarity(spi_base, spi_chip_sel, 0);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
case 2:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 3:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
}
spi_set_bits_per_transfer(spi_base, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_configure_cs_behavior(spi_base, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_baudrate_div(spi_base, spi_chip_sel, (sysclk_get_peripheral_hz() / spi_freq));
spi_set_delay_between_chip_select(spi_base, 0x10);
spi_set_transfer_delay(spi_base, spi_chip_sel, 0x01, 0x10);
spi_enable(spi_base);
return _spi;
}
/**
* \brief Set up an SPI device.
*
* The returned device descriptor structure must be passed to the driver
* whenever that device should be used as current slave device.
*
* \param p_spi Base address of the SPI instance.
* \param device Pointer to SPI device struct that should be initialized.
* \param flags SPI configuration flags. Common flags for all
* implementations are the SPI modes SPI_MODE_0 ...
* SPI_MODE_3.
* \param baud_rate Baud rate for communication with slave device in Hz.
* \param sel_id Board specific select id.
*/
void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
sel_id = sel_id;
spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_bits_per_transfer(p_spi, device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
spi_set_baudrate_div(p_spi, device->id,
spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(p_spi, device->id, flags >> 1);
spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
void cph_deca_spi_init(void)
{
freertos_spi_if spi_if;
const freertos_peripheral_options_t driver_options = {
/* No receive buffer pointer needed for SPI */
NULL,
/* No receive buffer size needed for SPI */
0,
/* Cortex-M4 priority */
configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY,
/* Operation mode - MASTER */
SPI_MASTER,
/* Blocking (not async) */
(USE_TX_ACCESS_MUTEX | USE_RX_ACCESS_MUTEX | WAIT_TX_COMPLETE | WAIT_RX_COMPLETE) };
spi_if = freertos_spi_master_init(DW_SPI, &driver_options);
if (spi_if != NULL) {
pio_configure_pin(DW_MISO_PIO_IDX, DW_MISO_PERIPH); // MISO
pio_configure_pin(DW_MOSI_PIO_IDX, DW_MOSI_PERIPH); // MOSI
pio_configure_pin(DW_SPCK_PIO_IDX, DW_SPCK_PERIPH); // SPCK
pio_configure_pin(DW_CSn_PIO_IDX, DW_CSn_PIO_PERIPH);
pmc_enable_periph_clk(ID_SPI);
spi_disable(DW_SPI);
spi_set_clock_polarity(DW_SPI, DW_CHIP_SELECT, DW_CLOCK_POLARITY);
spi_set_clock_phase(DW_SPI, DW_CHIP_SELECT, DW_CLOCK_PHASE);
spi_set_baudrate_div(DW_SPI, DW_CHIP_SELECT, (sysclk_get_cpu_hz() / DW_SPI_BAUD_SLOW));
spi_set_transfer_delay(DW_SPI, DW_CHIP_SELECT, DW_DELAY_BEFORE, DW_DELAY_BETWEEN);
// spi_configure_cs_behavior(DW_SPI, DW_CHIP_SELECT, SPI_CS_KEEP_LOW);
spi_configure_cs_behavior(DW_SPI, DW_CHIP_SELECT, SPI_CS_RISE_NO_TX);
spi_set_peripheral_chip_select_value(DW_SPI, DW_CHIP_SELECT_VALUE);
spi_enable(DW_SPI);
}
// return spi_if;
}
/**
* \brief Set up an SPI device.
*
* The returned device descriptor structure must be passed to the driver
* whenever that device should be used as current slave device.
*
* \param p_spi Base address of the SPI instance.
* \param device Pointer to SPI device struct that should be initialized.
* \param flags SPI configuration flags. Common flags for all
* implementations are the SPI modes SPI_MODE_0 ...
* SPI_MODE_3.
* \param baud_rate Baud rate for communication with slave device in Hz.
* \param sel_id Board specific select id.
*/
void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz());
/* avoid Cppcheck Warning */
UNUSED(sel_id);
if (-1 == baud_div) {
Assert(0 == "Failed to find baudrate divider");
}
spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_bits_per_transfer(p_spi, device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
spi_set_baudrate_div(p_spi, device->id, baud_div);
spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(p_spi, device->id, flags >> 1);
spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
/**
* \brief Set up an SPI device.
*
* The returned device descriptor structure must be passed to the driver
* whenever that device should be used as current slave device.
*
* \param p_spi Base address of the SPI instance.
* \param device Pointer to SPI device struct that should be initialized.
* \param flags SPI configuration flags. Common flags for all
* implementations are the SPI modes SPI_MODE_0 ...
* SPI_MODE_3.
* \param baud_rate Baud rate for communication with slave device in Hz.
* \param sel_id Board specific select id.
*/
void spi_master_setup_device(Spi *p_spi, const struct spi_device *device,
spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
/* avoid Cppcheck Warning */
UNUSED(sel_id);
UNUSED(flags);
spi_reset(p_spi);
spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_bits_per_transfer(p_spi, device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
int16_t baud_div = spi_calc_baudrate_div(baud_rate, SystemCoreClock);
spi_set_baudrate_div(p_spi, device->id, baud_div);
spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(p_spi, device->id, flags >> 1);
spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
/*
* Initialise the SPI interface as a MASTER
*
*/
void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS);
spi_set_fixed_peripheral_select(SPI_MASTER_BASE);
spi_disable_peripheral_select_decode(SPI_MASTER_BASE);
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_configure_cs_behavior(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_enable(SPI_MASTER_BASE);
}
/*
* Configure the SPI hardware, including SPI clock speed, mode, delays, chip select pins
* It uses values listed in
*/
void AJ_WSL_SPI_InitializeSPIController(void)
{
uint32_t config;
/* Initialize and enable DMA controller. */
pmc_enable_periph_clk(ID_DMAC);
dmac_init(DMAC);
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
dmac_enable(DMAC);
/* Configure DMA TX channel. */
config = 0;
config |= DMAC_CFG_DST_PER(AJ_SPI_TX_INDEX) |
DMAC_CFG_DST_H2SEL |
DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, AJ_DMA_TX_CHANNEL, config);
/* Configure DMA RX channel. */
config = 0;
config |= DMAC_CFG_SRC_PER(AJ_SPI_RX_INDEX) |
DMAC_CFG_SRC_H2SEL |
DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, AJ_DMA_RX_CHANNEL, config);
/* Enable receive channel interrupt for DMAC. */
uint8_t* interruptEnableAddress = AJ_SPI_ISER1_IEN_ADDR;
*interruptEnableAddress = AJ_SPI_DMAC_IEN_BIT;
dmac_enable_interrupt(DMAC, (1 << AJ_DMA_RX_CHANNEL));
dmac_enable_interrupt(DMAC, (1 << AJ_DMA_TX_CHANNEL));
//AJ_WSL_DMA_Setup();
dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL);
dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL);
/*
* Configure the hardware to enable SPI and some output pins
*/
{
pmc_enable_periph_clk(ID_PIOA);
pmc_enable_periph_clk(ID_PIOB);
pmc_enable_periph_clk(ID_PIOC);
pmc_enable_periph_clk(ID_PIOD);
// make all of these pins controlled by the right I/O controller
pio_configure_pin_group(PIOA, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_A);
pio_configure_pin_group(PIOB, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_B);
pio_configure_pin_group(PIOC, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_C);
pio_configure_pin_group(PIOD, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_D);
/*
* Reset the device by toggling the CHIP_POWER
*/
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_LOW);
AJ_Sleep(10);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_HIGH);
/*
* Reset the device by toggling the CHIP_PWD# signal
*/
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_LOW);
AJ_Sleep(10);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_HIGH);
/* configure the pin that detects SPI data ready from the target chip */
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_DIR_INPUT);
ioport_set_pin_sense_mode(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_SENSE_LEVEL_LOW);
pio_handler_set(PIOC, ID_PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT, (PIO_PULLUP | PIO_IT_FALL_EDGE), &AJ_WSL_SPI_CHIP_SPI_ISR);
pio_handler_set_priority(PIOD, (IRQn_Type) ID_PIOC, 0xB);
pio_enable_interrupt(PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT);
}
spi_enable_clock(AJ_WSL_SPI_DEVICE);
spi_reset(AJ_WSL_SPI_DEVICE);
spi_set_lastxfer(AJ_WSL_SPI_DEVICE);
spi_set_master_mode(AJ_WSL_SPI_DEVICE);
spi_disable_mode_fault_detect(AJ_WSL_SPI_DEVICE);
spi_set_peripheral_chip_select_value(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS);
spi_set_clock_polarity(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_POLARITY);
spi_set_clock_phase(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_PHASE);
spi_set_bits_per_transfer(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, (sysclk_get_cpu_hz() / AJ_WSL_SPI_CLOCK_RATE));
spi_set_transfer_delay(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_DELAY_BEFORE_CLOCK, AJ_WSL_SPI_DELAY_BETWEEN_TRANSFERS);
spi_set_fixed_peripheral_select(AJ_WSL_SPI_DEVICE);
spi_configure_cs_behavior(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CS_RISE_FORCED);
spi_enable_interrupt(AJ_WSL_SPI_DEVICE, SPI_IER_TDRE | SPI_IER_RDRF);
spi_enable(AJ_WSL_SPI_DEVICE);
}
// Here should be all the initialization functions for the module before 12v power
void init_module_peripherals_bp(void)
{
/* LEDs IO */
pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
/* Pulse inputs/state & d reset output */
pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_DET_PIO_ID);
ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_DET_PIO_ID);
ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID);
ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID);
ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID);
ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID);
ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Sload */
pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID);
ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Delay enables */
pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
// Init LED interrupt,
uint32_t ul_div;
uint32_t ul_tcclks;
/* Get system clock. */
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC1);
/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20);
/* Configure and enable interrupt on RC compare. */
tc_start(TC0, 1);
NVIC_DisableIRQ(TC1_IRQn);
NVIC_ClearPendingIRQ(TC1_IRQn);
//NVIC_SetPriority(TC1_IRQn, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC1);
tc_enable_interrupt(TC0, 1, TC_IER_CPCS);
/* SPI interface */
gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
//gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software
/* Configure an SPI peripheral. */
spi_enable_clock(SPI0);
spi_disable(SPI0);
spi_reset(SPI0);
spi_set_lastxfer(SPI0);
spi_set_master_mode(SPI0);
spi_disable_mode_fault_detect(SPI0);
/* Set variable chip select */
spi_set_variable_peripheral_select(SPI0);
/* Configure delay SPI channel */
spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT);
spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Configure RF atten SPI channel */
spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT);
spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Enable SPI */
spi_enable(SPI0);
}
void board_init(void)
{
ioport_init();
//SPI interface initialization
#ifdef CONF_SPI
//MISO
ioport_set_pin_peripheral_mode(PIN_PA21, IOPORT_MODE_MUX_A);
//MOSI
ioport_set_pin_peripheral_mode(PIN_PA22, IOPORT_MODE_MUX_A);
//SCK
ioport_set_pin_peripheral_mode(PIN_PA23, IOPORT_MODE_MUX_A);
//CS0
ioport_set_pin_peripheral_mode(PIN_PA24, IOPORT_MODE_MUX_A);
//CS1
ioport_set_pin_peripheral_mode(PIN_PA13, IOPORT_MODE_MUX_C);
//CS2
ioport_set_pin_peripheral_mode(PIN_PA14, IOPORT_MODE_MUX_C);
//CS3
ioport_set_pin_peripheral_mode(PIN_PB12, IOPORT_MODE_MUX_B);
spi_enable_clock(SPI);
spi_disable(SPI);
spi_reset(SPI);
spi_set_master_mode(SPI);
spi_disable_mode_fault_detect(SPI);
spi_disable_loopback(SPI);
spi_set_variable_peripheral_select(SPI);
spi_disable_peripheral_select_decode(SPI);
//spi_set_peripheral_chip_select_value(SPI, SPI_CHSEL);
//spi_set_transfer_delay(SPI, 1, 50, 0);
//spi_set_delay_between_chip_select(SPI, 0);
for(char i = 0; i < 4; i++){
spi_set_bits_per_transfer(SPI, i, 8);
//spi_set_baudrate_div(SPI, i, spi_calc_baudrate_div(1000000, sysclk_get_cpu_hz()));
spi_set_baudrate_div(SPI, i, (sysclk_get_cpu_hz() / 500000));
spi_configure_cs_behavior(SPI, i, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI, i, 0);
spi_set_clock_phase(SPI, i, 0);
}
spi_enable(SPI);
#endif
//USART0 initialization
#ifdef CONF_USART0
//USART0 RXD
ioport_set_pin_peripheral_mode(PIN_PA11, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART0);
#endif
//USART0 configuration struct
const sam_usart_opt_t usart0_console_settings = {
CONF_USART_0_BAUDRATE,
CONF_USART_0_CHAR_LENGTH,
CONF_USART_0_PARITY,
CONF_USART_0_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART0, &usart0_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART0);
usart_enable_rx(USART0);
usart_enable_interrupt(USART0, US_IER_RXRDY);
NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART0_IRQn);
#endif
//USART1 initialization
#ifdef CONF_USART1
//USART1 TXD
ioport_set_pin_peripheral_mode(PIN_PA16, IOPORT_MODE_MUX_A);
//USART1 RXD
ioport_set_pin_peripheral_mode(PIN_PA15, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART1);
#endif
//USART1 configuration struct
const sam_usart_opt_t usart1_console_settings = {
CONF_USART_1_BAUDRATE,
CONF_USART_1_CHAR_LENGTH,
CONF_USART_1_PARITY,
CONF_USART_1_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART1, &usart1_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART1);
usart_enable_rx(USART1);
usart_enable_interrupt(USART1, US_IER_RXRDY);
//NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART1_IRQn);
#endif
#ifdef CONF_TWIMS1
//SDA
ioport_set_pin_peripheral_mode(PIN_PB00, IOPORT_MODE_MUX_A);
//SCL
ioport_set_pin_peripheral_mode(PIN_PB01, IOPORT_MODE_MUX_A);
/* Set TWIM options */
uint32_t cpu_speed = 0;
cpu_speed = sysclk_get_peripheral_bus_hz(EXAMPLE_TWIM);
struct twim_config opts = {
.twim_clk = sysclk_get_cpu_hz(), //Importante
.speed = TWIM_MASTER_SPEED,
.hsmode_speed = 0,
.data_setup_cycles = 0,
.hsmode_data_setup_cycles = 0,
.smbus = false,
.clock_slew_limit = 0,
.clock_drive_strength_low = 0,
.data_slew_limit = 0,
.data_drive_strength_low = 0,
.hs_clock_slew_limit = 0,
.hs_clock_drive_strength_high = 0,
.hs_clock_drive_strength_low = 0,
.hs_data_slew_limit = 0,
.hs_data_drive_strength_low = 0,
};
/* Initialize the TWIM Module */
twim_set_callback(EXAMPLE_TWIM, 0, twim_default_callback, 1);
twim_set_config(EXAMPLE_TWIM, &opts);
#endif
//ADS 1294R initialization
#ifdef CONF_ADS
ADS_ioconfig();
Soft_Reset_ADS1298();
delay_us(50);
Stop_Read_Data_Continuous();
/*Configuration register 1*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_1_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x06);
/*Configuration register 2*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_2_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Configuration register 3*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_3_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0xDC);
/*Channel 1 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_1_SET_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 2 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_2_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 3 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_3_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*RLD_SENSP register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*RLD_SENSN register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*Respiration control register*/
//Respiration channel not enabled
#endif
}
