int main()
{
int len;
putstr("SPI flash programmer\n");
#ifdef SERIALLOAD
len = serial_load((void *) 0x00100000);
spi_flash_program((void *) 0x00100000, 0, len);
#else
spi_flash_program((void *) 0x00100000, 0, len);
#endif
putstr("Done\n");
return 0;
}
int main(int argc, char *argv[]) {
uint16_t i, t;
uint8_t buf[260];
const uint8_t testdata[] = {0xDE, 0xAD, 0xBE, 0xEF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C};
hal_disable_ints(); // In case we got here via jmp 0x0
// spi_init();
hal_uart_init();
// clocks_init(); //set up AD9510, enable FPGA clock @ 1x divisor
puts("SPI Flash test\n");
puts("Initializing SPI\n");
spif_init();
delay(800000);
puts("Erasing sector 1\n");
spi_flash_erase(0x00010000, 256);
delay(800000);
puts("Reading back data\n");
spi_flash_read(0x00010000, 256, buf);
delay(800000);
t=1;
for(i=4; i<250; i++) {
if(buf[i] != 0xFF) t=0;
}
if(!t) puts("Data was not initialized to 0xFF. Unsuccessful erase or read\n");
else puts("Data initialized to 0xFF, erase confirmed\n");
puts("Writing test buffer\n");
spi_flash_program(0x00010000, 16, testdata);
//memset(buf, 0, 256);
delay(800000);
puts("Wrote data, reading back\n");
spi_flash_read(0x00010000, 16, buf);
if(memcmp(testdata, buf, 16)) puts("Data is not the same between read and write. Unsuccessful write or read\n");
else puts("Successful write! Flash write correct\n");
return 0;
}
void uart_flash_loader(void) {
char buf[256]; //input data buffer
uint8_t ihx[32]; //ihex data buffer
uint32_t slot_offset = PROD_FW_IMAGE_LOCATION_ADDR; //initial slot offset to program to.
uint32_t extended_addr = 0x00000000; //extended Intel hex segment address
size_t sector_size = spi_flash_log2_sector_size();
ihex_record_t ihex_record;
ihex_record.data = ihx;
int i;
//not gonna win a turing prize for my C text parsing
while(1) {
gets(buf);
if(!strncmp(buf, "!SECTORSIZE", 7)) { //return the sector size in log format
putstr("OK ");
puthex8((uint32_t) sector_size); //err, this should probably be decimal for human readability. we do have itoa now...
putstr("\n");
}
else if(!strncmp(buf, "!SETADDR", 7)) { //set start address for programming
slot_offset = atol(&buf[8]);
puts("OK");
// puthex32(slot_offset);
// putstr("\n");
}
else if(!strncmp(buf, "!ERASE", 6)) { //erase a sector
uint32_t sector = atol(&buf[6]);
uint32_t size = 2 << (sector_size-1);
uint32_t addr = sector << sector_size;
spi_flash_erase(addr, size); //we DO NOT implement write protection here. it is up to the HOST PROGRAM to not issue an ERASE unless it means it.
//unfortunately the Flash cannot write-protect the segments that really matter, so we only use global write-protect
//as a means of avoiding accidental writes from runaway code / garbage on the SPI bus.
puts("OK");
}
//can't exactly run firmware if you're already executing out of main RAM
/* else if(!strncmp(buf, "!RUNSFW", 7)) {
if(is_valid_fw_image(SAFE_FW_IMAGE_LOCATION_ADDR)) {
puts("OK");
spi_flash_read(SAFE_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES, (void *)RAM_BASE);
start_program(RAM_BASE);
} else {
puts("NOK");
}
}
else if(!strncmp(buf, "!RUNPFW", 7)) {
if(is_valid_fw_image(PROD_FW_IMAGE_LOCATION_ADDR)) {
puts("OK");
spi_flash_read(PROD_FW_IMAGE_LOCATION_ADDR, FW_IMAGE_SIZE_BYTES-1, (void *)RAM_BASE);
start_program(RAM_BASE);
} else {
puts("NOK");
}
}
*/
else if(!strncmp(buf, "!RUNPFPGA", 8)) {
if(is_valid_fpga_image(PROD_FPGA_IMAGE_LOCATION_ADDR)) {
puts("OK");
//icap_reload_fpga(PROD_FPGA_IMAGE_LOCATION_ADDR);
} else {
puts("NOK");
}
}
else if(!strncmp(buf, "!RUNSFPGA", 8)) {
if(is_valid_fpga_image(SAFE_FPGA_IMAGE_LOCATION_ADDR)) {
puts("OK");
//icap_reload_fpga(SAFE_FPGA_IMAGE_LOCATION_ADDR);
} else {
puts("NOK");
}
}
else if(!strncmp(buf, "!READ", 5)) {
uint32_t addr = atol(&buf[5]);
spi_flash_read(addr, 16, ihx);
for(i=0; i < 16; i++) {
puthex8(ihx[i]);
}
putstr("\n");
}
else if(!ihex_parse(buf, &ihex_record)) { //last, try to see if the input was a valid IHEX line
switch (ihex_record.type) {
case 0:
spi_flash_program(ihex_record.addr + slot_offset + extended_addr, ihex_record.length, ihex_record.data);
puts("OK");
break;
case 1:
//here we would expect a CRC checking or something else to take place. for now we do nothing.
//well, we set the extended segment addr back to 0
extended_addr = 0;
puts("DONE");
break;
case 4:
//set the upper 16 bits of the address
extended_addr = ((ihex_record.data[0] << 8) + ihex_record.data[1]) << 16;
puts("OK");
break;
default:
puts("NOK");
}
}
else puts("NOK");
} //while(1)
}
//Firmware update packet handler
void handle_udp_fw_update_packet(struct socket_address src, struct socket_address dst,
unsigned char *payload, int payload_len) {
const usrp2_fw_update_data_t *update_data_in = (usrp2_fw_update_data_t *) payload;
usrp2_fw_update_data_t update_data_out;
usrp2_fw_update_id_t update_data_in_id = update_data_in->id;
//ensure that the protocol versions match
/* if (payload_len >= sizeof(uint32_t) && update_data_in->proto_ver != USRP2_FW_COMPAT_NUM){
printf("!Error in update packet handler: Expected compatibility number %d, but got %d\n",
USRP2_FW_COMPAT_NUM, update_data_in->proto_ver
);
update_data_in_id = USRP2_FW_UPDATE_ID_OHAI_LOL; //so we can respond
}
*/
//ensure that this is not a short packet
if (payload_len < sizeof(usrp2_fw_update_data_t)){
printf("!Error in update packet handler: Expected payload length %d, but got %d\n",
(int)sizeof(usrp2_fw_update_data_t), payload_len
);
update_data_in_id = USRP2_FW_UPDATE_ID_WAT;
}
switch(update_data_in_id) {
case USRP2_FW_UPDATE_ID_OHAI_LOL: //why hello there you handsome devil
update_data_out.id = USRP2_FW_UPDATE_ID_OHAI_OMG;
memcpy(&update_data_out.data.ip_addr, (void *)get_ip_addr(), sizeof(struct ip_addr));
//this is to stop streaming for the folks who think updating while streaming is a good idea
sr_rx_ctrl0->cmd = 1 << 31 | 1 << 28; //no samples now
sr_rx_ctrl0->time_secs = 0;
sr_rx_ctrl0->time_ticks = 0; //latch the command
sr_rx_ctrl1->cmd = 1 << 31 | 1 << 28; //no samples now
sr_rx_ctrl1->time_secs = 0;
sr_rx_ctrl1->time_ticks = 0; //latch the command
sr_tx_ctrl->cyc_per_up = 0;
break;
case USRP2_FW_UPDATE_ID_WATS_TEH_FLASH_INFO_LOL: //query sector size, memory size so the host can mind the boundaries
update_data_out.data.flash_info_args.sector_size_bytes = spi_flash_sector_size();
update_data_out.data.flash_info_args.memory_size_bytes = spi_flash_memory_size();
update_data_out.id = USRP2_FW_UPDATE_ID_HERES_TEH_FLASH_INFO_OMG;
break;
case USRP2_FW_UPDATE_ID_I_CAN_HAS_HW_REV_LOL: //get the hardware revision of the platform for validation checking
update_data_out.data.hw_rev = (uint32_t) get_hw_rev();
update_data_out.id = USRP2_FW_UPDATE_ID_HERES_TEH_HW_REV_OMG;
break;
case USRP2_FW_UPDATE_ID_ERASE_TEH_FLASHES_LOL: //out with the old
spi_flash_async_erase_start(&spi_flash_async_state, update_data_in->data.flash_args.flash_addr, update_data_in->data.flash_args.length);
update_data_out.id = USRP2_FW_UPDATE_ID_ERASING_TEH_FLASHES_OMG;
break;
case USRP2_FW_UPDATE_ID_R_U_DONE_ERASING_LOL:
//poll for done, set something in the reply packet
//spi_flash_async_erase_poll() also advances the state machine, so you should call it reasonably often to get things done quicker
if(spi_flash_async_erase_poll(&spi_flash_async_state)) update_data_out.id = USRP2_FW_UPDATE_ID_IM_DONE_ERASING_OMG;
else update_data_out.id = USRP2_FW_UPDATE_ID_NOPE_NOT_DONE_ERASING_OMG;
break;
case USRP2_FW_UPDATE_ID_WRITE_TEH_FLASHES_LOL: //and in with the new
//spi_flash_program() goes pretty quick compared to page erases, so we don't bother polling -- it'll come back in some milliseconds
//if it doesn't come back fast enough, we'll just write smaller packets at a time until it does
spi_flash_program(update_data_in->data.flash_args.flash_addr, update_data_in->data.flash_args.length, update_data_in->data.flash_args.data);
update_data_out.id = USRP2_FW_UPDATE_ID_WROTE_TEH_FLASHES_OMG;
break;
case USRP2_FW_UPDATE_ID_READ_TEH_FLASHES_LOL: //for verify
spi_flash_read(update_data_in->data.flash_args.flash_addr, update_data_in->data.flash_args.length, update_data_out.data.flash_args.data);
update_data_out.id = USRP2_FW_UPDATE_ID_KK_READ_TEH_FLASHES_OMG;
break;
case USRP2_FW_UPDATE_ID_RESET_MAH_COMPUTORZ_LOL: //for if we ever get the ICAP working
//should reset via icap_reload_fpga(uint32_t flash_address);
update_data_out.id = USRP2_FW_UPDATE_ID_RESETTIN_TEH_COMPUTORZ_OMG;
//you should note that if you get a reply packet to this the reset has obviously failed
icap_reload_fpga(0);
break;
// case USRP2_FW_UPDATE_ID_KTHXBAI: //see ya
// break;
default: //uhhhh
update_data_out.id = USRP2_FW_UPDATE_ID_WAT;
}
send_udp_pkt(USRP2_UDP_UPDATE_PORT, src, &update_data_out, sizeof(update_data_out));
}
