int main(void) {
unsigned short addr1 = 0x1234; // the address for writing the ram
char data[] = "Help, I'm stuck in the RAM!"; // the test message
char read[] = "***************************"; // buffer for reading from ram
char buf[100]; // buffer for comm. with the user
unsigned char status; // used to verify we set the status
NU32_Startup(); // cache on, interrupts on, LED/button init, UART init
ram_init();
// check the ram status
CS = 0;
spi_io(0x5); // ram read status command
status = spi_io(0); // the actual status
CS = 1;
sprintf(buf, "Status 0x%x\r\n",status);
NU32_WriteUART3(buf);
sprintf(buf,"Writing \"%s\" to ram at address 0x%x\r\n", data, addr1);
NU32_WriteUART3(buf);
// write the data to the ram
ram_write(addr1, data, strlen(data) + 1); // +1, to send the '\0' character
ram_read(addr1, read, strlen(data) + 1); // read the data back
sprintf(buf,"Read \"%s\" from ram at address 0x%x\r\n", read, addr1);
NU32_WriteUART3(buf);
while(1) {
;
}
return 0;
}
void setVoltage(char channel, unsigned int voltage) {
// int dig_vol = 0;
// int data_sent = 0;
// dig_vol = (2^8 * floor(voltage / 3.3));
switch(channel) {
case 'A' :
//data_sent = 0x7000 | (dig_vol<<4);
//data_sent = 0x70 | (voltage>>4);
CS = 0;
spi_io(0x70 | (voltage>>4));
spi_io(voltage<<4);
CS = 1;
break;
case 'B' :
//data_sent = 0xF000 | (dig_vol<<4);
//data_sent = 0xF000 | (voltage<<4);
CS = 0;
spi_io(0xF0 | (voltage>>4));
spi_io(voltage<<4);
CS = 1;
break;
}
// CS = 0;
// spi_io(data_sent & 0xFF00>> 8); // the most significant byte
// spi_io(data_sent & 0x00FF); // the least significant byte
// CS = 1;
}
// initialize spi4 and the ram module
void ram_init() {
// set up the chip select pin as an output
// the chip select pin is used by the sram to indicate
// when a command is beginning (clear CS to low) and when it
// is ending (set CS high)
TRISBbits.TRISB8 = 0;
CS = 1;
// Master - SPI4, pins are: SDI4(F4), SDO4(F5), SCK4(F13).
// we manually control SS4 as a digital output (F12)
// since the pic is just starting, we know that spi is off. We rely on defaults here
// setup spi4
SPI4CON = 0; // turn off the spi module and reset it
SPI4BUF; // clear the rx buffer by reading from it
SPI4BRG = 0x3; // baud rate to 10 MHz [SPI4BRG = (80000000/(2*desired))-1]
SPI4STATbits.SPIROV = 0; // clear the overflow bit
SPI4CONbits.CKE = 1; // data changes when clock goes from hi to lo (since CKP is 0)
SPI4CONbits.MSTEN = 1; // master operation
SPI4CONbits.ON = 1; // turn on spi 4
// send a ram set status command.
CS = 0; // enable the ram
spi_io(0x01); // ram write status
spi_io(0x41); // sequential mode (mode = 0b01), hold disabled (hold = 0)
CS = 1; // finish the command
}
unsigned char radio_write_register(unsigned char reg, unsigned char data)
{
unsigned char status;
CS = 0; // bring CS low to activate SPI
status = spi_io(reg); // send cmd & retrieve radio's status
spi_io(data);
CS = 1; // complete the command
return status;
}
void wiz_low_write(u16 addr, u08 value)
{
spi_low_enable_cs(SPI_WIZ_CS_MASK);
spi_io(WIZ_OP_WRITE);
spi_io(addr >> 8);
spi_io(addr & 0xff);
spi_io(value);
spi_low_disable_cs(SPI_WIZ_CS_MASK);
}
u08 wiz_low_read(u16 addr)
{
spi_low_enable_cs(SPI_WIZ_CS_MASK);
spi_io(WIZ_OP_READ);
spi_io(addr >> 8);
spi_io(addr & 0xff);
u08 result = spi_io(0);
spi_low_disable_cs(SPI_WIZ_CS_MASK);
return result;
}
// write len bytes to the ram, starting at the address addr
void ram_write(unsigned short addr, const char data[], int len) {
int i = 0;
CS = 0; // enable the ram by lowering the chip select line
spi_io(0x2); // sequential write operation
spi_io((addr & 0xFF00) >> 8 ); // most significant byte of address
spi_io(addr & 0x00FF); // the least significant address byte
for(i = 0; i < len; ++i) {
spi_io(data[i]);
}
CS = 1; // raise the chip select line, ending communication
}
// read len bytes from ram, starting at the address addr
void ram_read(unsigned short addr, char data[], int len) {
int i = 0;
CS = 0;
spi_io(0x3); // ram read operation
spi_io((addr & 0xFF00) >> 8); // most significant address byte
spi_io(addr & 0x00FF); // least significant address byte
for(i = 0; i < len; ++i) {
data[i] = spi_io(0); // read in the data
}
CS = 1;
}
void spi_write (uint8_t addr, uint8_t data)
{
spi_cs_l();
spi_io(0x02); /* WRITE DATA */
spi_io(addr);
spi_io(data);
spi_cs_h();
}
int main(void)
{
/*
* pgm_read_byte gets cached and there doesn't seem to be any other
* way to dissuade gcc from doing this.
*/
volatile int zero = 0;
uint32_t loop = 0;
board_init();
spi_init();
_delay_ms(10);
/* set MCP2515 clkdiv to /2 for 8MHz */
can_cs_l();
spi_io(INSTRUCTION_WRITE);
spi_io(CANCTRL);
spi_io(0x85);
can_cs_h();
led_init();
usb_init();
dfu_init();
/* move interrupt vectors to the boot loader */
MCUCR = 1 << IVCE;
MCUCR = 1 << IVSEL;
sei();
while (loop < 5) {
led_a_on();
led_b_on();
_delay_ms(50);
led_a_off();
led_b_off();
_delay_ms(400);
if (dfu.state == dfuIDLE && pgm_read_byte(zero) != 0xff)
loop++;
else
loop = 0;
}
cli();
usb_reset();
run_payload();
while (1);
}
// read data from the accelerometer, given the starting register address.
// return the data in data
void acc_read_register(unsigned char reg, unsigned char data[], unsigned int len) {
unsigned int i;
reg |= 0x80; // set the read bit (as per the accelerometer's protocol)
if(len > 1) {
reg |= 0x40; // set the address auto increment bit (as per the accelerometer's protocol)
}
CS = 0;
spi_io(reg);
for(i = 0; i != len; ++i) {
data[i] = spi_io(0); // read data from spi
}
CS = 1;
}
void greyScaleHack(uint8_t callNumber){
uint8_t x,colour,bits;
spi_obtain_bus(1);
pcdIO.assert_command();
pcdIO.assert_chip_delect();
spi_setup(SPI_DIVIDER_4, 0); //4 Mhz @ 16Mhz
spi_io(PCD8544_CMD_SET_Y);
spi_io(PCD8544_CMD_SET_X);
pcdIO.desert_command();
colour=0;
for (x=0; x<84; x++){
if (colour>callNumber) bits=0xff;
else bits=0;
spi_io(bits);
spi_io(bits);
spi_io(bits);
spi_io(bits);
spi_io(bits);
spi_io(bits);
if ((x&7)==0) colour++;
colour &= 3;
}
pcdIO.desert_chip_select();
spi_release_bus();
}
void spi_write_block (uint8_t addr, uint8_t * buf, uint8_t count)
{
uint8_t i;
spi_cs_l();
spi_io(0x02); /* WRITE DATA */
spi_io(addr);
for (i = 0; i < count; i++)
spi_io(buf[i]);
spi_cs_h();
}
void spi_read_block (uint8_t addr, uint8_t * buf, uint8_t count)
{
uint8_t i;
spi_cs_l();
spi_io(0x03); /* READ DATA */
spi_io(addr);
for (i = 0; i < count; i++)
buf[i] = spi_io(0xff);
spi_cs_h();
}
uint8_t spi_read (uint8_t addr)
{
uint8_t ret;
spi_cs_l();
spi_io(0x03); /* READ DATA */
spi_io(addr);
ret = spi_io(0xff);
spi_cs_h();
return ret;
}
void LCD_data16(unsigned short dat) {
LATBbits.LATB15 = 1; // DAT
LATBbits.LATB7 = 0; // CS
spi_io(dat>>8);
spi_io(dat);
LATBbits.LATB7 = 1; // CS
}
unsigned char radio_command(unsigned char reg)
{
unsigned char data;
CS = 0; // bring CS low to activate SPI
data = spi_io(reg); // send cmd & retrieve data
CS = 1; // complete the command
return data;
}
void setVoltage(char channel, unsigned char voltage) {
unsigned short buffer = 0x0;
buffer = buffer | channel << 15;
buffer = buffer | 0x7 << 12;
buffer = buffer | voltage << 4;
CS = 0;
spi_io((buffer & 0xFF00) >> 8);
spi_io(buffer & 0x00FF);
//LATAbits.LATA4 = !LATAbits.LATA4;
CS = 1;
}
void transmit_data(char *data_to_send, int n_bytes){
int counter;
radio_write_register(0x27, 0x7E); // Clear all FIFO interrupts and maximum number of retransmits
radio_write_register(0x20, 0x3A); // Power up to change to change to STAND BY state
radio_command(0xE1); // Clear TX fifo, the data sheet says that this is supposed to come up 0 after POR, but that doesn't seem to be the case
CS = 0;
spi_io(0xA0);
for (counter = 0; counter < n_bytes; counter++)
{
spi_io(data_to_send[counter]);
}
CS = 1;
CE = 1; //Pulse CE to start transmission
for (counter = 0; counter < 800000; counter++){;} // Wait for 1 ms (assuming the PIC clock is set to 80MHz)
CE = 0;
}
void LCD_data(unsigned char dat) {
LATBbits.LATB15 = 1; // DAT
LATBbits.LATB7 = 0; // CS
spi_io(dat);
LATBbits.LATB7 = 1; // CS
}
void LCD_command(unsigned char com) {
LATBbits.LATB15 = 0; // DAT
LATBbits.LATB7 = 0; // CS
spi_io(com);
LATBbits.LATB7 = 1; // CS
}
// every 1ms
void timer_interrupt(void)
{
static UBYTE skip_discrete;
static UBYTE discrete_tx = 0x04;
FMDSRBITS fmdsr;
FMDCRBITS fmdcr;
// come back in another 1ms
MATCH += 32;
// irq tics
if (++status.irq_tics > 999)
{
status.irq_tics = 0;
status.seconds++;
status.flags.cts_update = TRUE;
if (status.transient_clk) status.transient_clk--;
}
// roc clock / flag update
if (status.roc_clk) status.roc_clk--;
else status.flags.roc_update = TRUE;
// iac clock / flag update
if (status.iac_clk) status.iac_clk--;
else status.flags.iac_update = TRUE;
// ego clock / flag update
if(status.ego_clk) status.ego_clk--;
else status.flags.ego_update = TRUE;
// COP reset for *this* cpu
COPLCK = 0xff;
COPCLK = 0x00;
// fetch discrete every 10ms
if (!skip_discrete--)
{
discrete_tx ^= 0x02;
discrete_tx &= 0x7f; // select discrete inputs
CHPSELbits.IICS = TRUE;
status.discrete = spi_io(discrete_tx) << 8;
discrete_tx |= 0x80; // select status byte
status.discrete |= spi_io(discrete_tx);
CHPSELbits.IICS = FALSE;
skip_discrete = 10;
}
fmdsr = FMDSRbits;
// was there an injection event over on the FMD?
if (fmdsr.INJ_OCCURRED)
{
status.flags.inj_occurred = TRUE;
if (!status.inj_clk)
{
INJPER = status.APW;
status.inj_clk = config.inj_skips;
if (status.asc_clk) status.asc_clk--;
}
else
{
INJPER = 0;
status.inj_clk--;
}
// acceleration enrichment
if (status.ae_clk)
{
status.ae_clk--;
status.AE.APW = interpolate_u16(status.ae_clk, 0, config.AE.cycles, 0, status.AE.BPW);
ASYNC = status.AE.APW;
asm("ldd 0x3ffc");
asm("oraa #0x04");
asm("jsr bus_delay");
asm("std 0x3ffc");
asm("anda #0xfb");
asm("jsr bus_delay");
asm("std 0x3ffc");
} else status.flags.accel = FALSE;
}
}
void acc_write_register(unsigned char reg, unsigned char data) {
CS = 0; // bring CS low to activate SPI
spi_io(reg);
spi_io(data);
CS = 1; // complete the command
}
