/* ser_phy API function */
uint32_t ser_phy_open(ser_phy_events_handler_t events_handler)
{
if (m_spi_master_state != SER_PHY_STATE_DISABLED)
{
return NRF_ERROR_INVALID_STATE;
}
if (events_handler == NULL)
{
return NRF_ERROR_NULL;
}
uint32_t err_code = NRF_SUCCESS;
ser_phy_init_gpio();
m_spi_master_state = SER_PHY_STATE_IDLE;
m_callback_events_handler = events_handler;
spi_master_config_t spi_master_config = SPI_MASTER_INIT_DEFAULT;
spi_master_config.SPI_Pin_SCK = SER_PHY_SPI_MASTER_PIN_SCK;
spi_master_config.SPI_Pin_MISO = SER_PHY_SPI_MASTER_PIN_MISO;
spi_master_config.SPI_Pin_MOSI = SER_PHY_SPI_MASTER_PIN_MOSI;
spi_master_config.SPI_Pin_SS = SER_PHY_SPI_MASTER_PIN_SLAVE_SELECT;
spi_master_config.SPI_PriorityIRQ = APP_IRQ_PRIORITY_MID;
err_code = spi_master_open(SER_PHY_SPI_MASTER, &spi_master_config);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
spi_master_evt_handler_reg(SER_PHY_SPI_MASTER, ser_phy_spi_master_event_handler);
ser_phy_init_gpiote();
ser_phy_init_PendSV();
return err_code;
}
void SPI_setup(void)
{
/* Disable chip select */
SetOutput(SDF_CS);
#ifdef SPI_MASTER_0_ENABLE
spi_master_hw_instance_t spi_master_instance = SPI_MASTER_0;
#elif defined(SPI_MASTER_1_ENABLE)
spi_master_hw_instance_t spi_master_instance = SPI_MASTER_1;
#endif
// spi_master_event_handler_t spi_master_event_handler = spi_master_0_event_handler;
uint32_t err_code = NRF_SUCCESS;
// Configure SPI master.
spi_master_config_t spi_config = SPI_MASTER_INIT_DEFAULT;
switch (spi_master_instance)
{
#ifdef SPI_MASTER_0_ENABLE
case SPI_MASTER_0:
{
spi_config.SPI_Pin_SCK = SCK; //SPIM0_SCK_PIN;
spi_config.SPI_Pin_MISO = DIN; //SPIM0_MISO_PIN;
spi_config.SPI_Pin_MOSI = DOUT; //SPIM0_MOSI_PIN;
spi_config.SPI_Pin_SS = SPI_PIN_DISCONNECTED; //SPIM0_SS_PIN; //SDF_CS
}
break;
#endif /* SPI_MASTER_0_ENABLE */
#ifdef SPI_MASTER_1_ENABLE
case SPI_MASTER_1:
{
spi_config.SPI_Pin_SCK = SCK; //SPIM1_SCK_PIN;
spi_config.SPI_Pin_MISO = DIN; //SPIM1_MISO_PIN;
spi_config.SPI_Pin_MOSI = DOUT; //SPIM1_MOSI_PIN;
spi_config.SPI_Pin_SS = SPI_PIN_DISCONNECTED; //SPIM1_SS_PIN; //SDF_CS
}
break;
#endif /* SPI_MASTER_1_ENABLE */
default:
break;
}
spi_config.SPI_PriorityIRQ = APP_IRQ_PRIORITY_LOW;
spi_config.SPI_CONFIG_ORDER = SPI_CONFIG_ORDER_MsbFirst;
spi_config.SPI_CONFIG_CPOL = SPI_CONFIG_CPOL_ActiveLow;
spi_config.SPI_CONFIG_CPHA = SPI_CONFIG_CPHA_Trailing;
err_code = spi_master_open(spi_master_instance, &spi_config);
APP_ERROR_CHECK(err_code);
#ifdef SPI_MASTER_0_ENABLE
// Register event handler for SPI master.
spi_master_evt_handler_reg(spi_master_instance, spi_master_0_event_handler);
#elif defined(SPI_MASTER_1_ENABLE)
// Register event handler for SPI master.
spi_master_evt_handler_reg(spi_master_instance, spi_master_1_event_handler);
#endif
}
/**@brief Function for initializing a SPI master driver.
*
* @param[in] spi_master_instance An instance of SPI master module.
* @param[in] spi_master_event_handler An event handler for SPI master events.
* @param[in] lsb Bits order LSB if true, MSB if false.
*/
static void spi_master_init(spi_master_hw_instance_t spi_master_instance,
spi_master_event_handler_t spi_master_event_handler,
const bool lsb)
{
uint32_t err_code = NRF_SUCCESS;
// Configure SPI master.
spi_master_config_t spi_config = SPI_MASTER_INIT_DEFAULT;
switch (spi_master_instance)
{
#ifdef SPI_MASTER_0_ENABLE
case SPI_MASTER_0:
{
spi_config.SPI_Pin_SCK = SPIM0_SCK_PIN;
spi_config.SPI_Pin_MISO = SPIM0_MISO_PIN;
spi_config.SPI_Pin_MOSI = SPIM0_MOSI_PIN;
spi_config.SPI_Pin_SS = SPIM0_SS_PIN;
}
break;
#endif /* SPI_MASTER_0_ENABLE */
#ifdef SPI_MASTER_1_ENABLE
case SPI_MASTER_1:
{
spi_config.SPI_Pin_SCK = SPIM1_SCK_PIN;
spi_config.SPI_Pin_MISO = SPIM1_MISO_PIN;
spi_config.SPI_Pin_MOSI = SPIM1_MOSI_PIN;
spi_config.SPI_Pin_SS = SPIM1_SS_PIN;
}
break;
#endif /* SPI_MASTER_1_ENABLE */
default:
break;
}
spi_config.SPI_CONFIG_ORDER = (lsb ? SPI_CONFIG_ORDER_LsbFirst : SPI_CONFIG_ORDER_MsbFirst);
err_code = spi_master_open(spi_master_instance, &spi_config);
APP_ERROR_CHECK(err_code);
// Register event handler for SPI master.
spi_master_evt_handler_reg(spi_master_instance, spi_master_event_handler);
}
/** @brief Function for initializing a SPI master driver.
*/
static uint32_t spi_master_init(void)
{
spi_master_config_t spi_config = SPI_MASTER_INIT_DEFAULT;
#if defined(SPI_MASTER_0_ENABLE)
spi_config.SPI_Pin_SCK = SPIM0_SCK_PIN;
spi_config.SPI_Pin_MISO = SPIM0_MISO_PIN;
spi_config.SPI_Pin_MOSI = SPIM0_MOSI_PIN;
spi_config.SPI_Pin_SS = SPIM0_SS_PIN;
#elif defined(SPI_MASTER_1_ENABLE)
spi_config.SPI_Pin_SCK = SPIM1_SCK_PIN;
spi_config.SPI_Pin_MISO = SPIM1_MISO_PIN;
spi_config.SPI_Pin_MOSI = SPIM1_MOSI_PIN;
spi_config.SPI_Pin_SS = SPIM1_SS_PIN;
#endif /* SPI_MASTER_ENABLE */
return spi_master_open(SPI_MASTER_HW, &spi_config);
}
/* ser_phy API function */
uint32_t ser_phy_open(ser_phy_events_handler_t events_handler)
{
if (m_spi_master_state != SER_PHY_STATE_DISABLED)
{
return NRF_ERROR_INVALID_STATE;
}
if (events_handler == NULL)
{
return NRF_ERROR_NULL;
}
uint32_t err_code = NRF_SUCCESS;
m_spi_master_state = SER_PHY_STATE_IDLE;
m_callback_events_handler = events_handler;
ser_phy_init_gpiote();
/* Configure SPI Master driver */
spi_master_config_t spi_master_config;
spi_master_config.SPI_Freq = SPI_FREQUENCY_FREQUENCY_M1;
spi_master_config.SPI_Pin_SCK = SER_PHY_SPI_MASTER_PIN_SCK;
spi_master_config.SPI_Pin_MISO = SER_PHY_SPI_MASTER_PIN_MISO;
spi_master_config.SPI_Pin_MOSI = SER_PHY_SPI_MASTER_PIN_MOSI;
spi_master_config.SPI_Pin_SS = SER_PHY_SPI_MASTER_PIN_SLAVE_SELECT;
spi_master_config.SPI_ORDER = SPI_CONFIG_ORDER_LsbFirst;
spi_master_config.SPI_CPOL = SPI_CONFIG_CPOL_ActiveHigh;
spi_master_config.SPI_CPHA = SPI_CONFIG_CPHA_Leading;
err_code = spi_master_open(SER_PHY_SPI_MASTER, &spi_master_config);
if (err_code != NRF_SUCCESS)
{
return err_code;
}
#ifdef _SPI_5W_
spi_5W_master_evt_handler_reg(SER_PHY_SPI_MASTER, ser_phy_spi_master_event_handler);
#else
spi_master_evt_handler_reg(SER_PHY_SPI_MASTER, ser_phy_spi_master_event_handler);
#endif
ser_phy_init_pendSV();
return err_code;
}
