void ledmatrix_update_column(uint8_t x, MatrixColumn col) {
(void)spi_send_byte(CMD_UPDATE_COL);
(void)spi_send_byte(x & 0x0F); // column number
for(uint8_t y = 0; y<MATRIX_NUM_ROWS; y++) {
(void)spi_send_byte(col[y]);
}
}
uint8_t iqrf_send_buff(uint8_t *iqrfTx, uint8_t len)
{
uint8_t stav = 0;
/* check SPI status max. 10 loops */
i = 0;
while (!iqrf_status()) {
i++;
if(i>=10)
goto end;
}
ptype = 0x80+len;
spi_send_byte(0xF0);
spi_send_byte(ptype);
crcm = 0x5F ^ 0xF0 ^ ptype;
/* payload */
for (i=0; i < len; i++) {
crcm ^= iqrfTx[i];
spi_send_byte(iqrfTx[i]);
}
spi_send_byte(crcm);
/* state should be 0x3E (CRC err) or 0x3F (CRC OK) */
stav = spi_transcieve_byte(0x00) - 0x3E;
end:
return stav;
}
void ledmatrix_update_row(uint8_t y, MatrixRow row) {
(void)spi_send_byte(CMD_UPDATE_ROW);
(void)spi_send_byte(y & 0x07); // row number
for(uint8_t x = 0; x<MATRIX_NUM_COLUMNS; x++) {
(void)spi_send_byte(row[x]);
}
}
/**
* \ingroup sd_raw
* Send a command to the memory card which responses with a R2 response.
*
* \param[in] command The command to send.
* \param[in] arg The argument for command.
* \returns The command answer.
*/
uint16_t sd_raw_send_command_r2(uint8_t command, uint32_t arg)
{
uint16_t response;
/* wait some clock cycles */
spi_rec_byte();
/* send command via SPI */
spi_send_byte(0x40 | command);
spi_send_byte((arg >> 24) & 0xff);
spi_send_byte((arg >> 16) & 0xff);
spi_send_byte((arg >> 8) & 0xff);
spi_send_byte((arg >> 0) & 0xff);
spi_send_byte(command == CMD_GO_IDLE_STATE ? 0x95 : 0xff);
/* receive response */
for(uint8_t i = 0; i < 10; ++i)
{
response = spi_rec_byte();
if(response != 0xff)
break;
}
response <<= 8;
response |= spi_rec_byte();
return response;
}
void ledmatrix_update_all(MatrixData data) {
(void)spi_send_byte(CMD_UPDATE_ALL);
for(uint8_t y=0; y<MATRIX_NUM_ROWS; y++) {
for(uint8_t x=0; x<MATRIX_NUM_COLUMNS; x++) {
(void)spi_send_byte(data[x][y]);
}
}
}
int sd_load_sector(UBYTE* target, DWORD sector)
{
DWORD address;
BYTE r;
BYTE timeout;
address = sector<<9;
#ifdef DEBUG_SD
debug_puts("loading address ");
debug_print_dword(address);
debug_puts("\n");
#endif
sd_wait_ready();
// read block
spi_assert_cs();
spi_send_byte(0x51); // CMD17
spi_send_byte((address>>24)&0xff);
spi_send_byte((address>>16)&0xff);
spi_send_byte((address>>8)&0xff);
spi_send_byte(address&0xff);
spi_send_byte(0xff);
r = sd_wait_r1();
#ifdef DEBUG_SD
debug_puts("cmd17:");
debug_print_byte(r);
debug_puts("\n");
#endif
if ((r&0x80)!=0) {
spi_deassert_cs();
return FALSE;
}
// wait for 0xfe (start of block)
timeout = 0xff;
while (spi_receive_byte()!=0xfe) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
// read block
load_data(target);
// skip crc
spi_delay();
spi_delay();
// shutdown
spi_delay();
spi_deassert_cs();
return TRUE;
}
void ld3320_write_reg(uint8 data1,uint8 data2)
{
CS_L();
SPIS_L();
spi_send_byte(0x04);
spi_send_byte(data1);
spi_send_byte(data2);
CS_H();
}
static void spi_write(ice1712_t *ice, unsigned int dev, unsigned int reg, unsigned int data)
{
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
spi_send_byte(ice, data); /* DATA */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
}
uint8 ld3320_read_reg(uint8 reg_add)
{
uint8 i;
CS_L();
SPIS_L();
spi_send_byte(0x05);
spi_send_byte(reg_add);
i=spi_send_byte(0);
CS_H();
return(i);
}
void display_send_byte(unsigned char byte)
{
DISPLAY_START_TRANSMIT();
spi_send_byte(byte);
DISPLAY_END_TRANSMIT();
}
void sd_delay(char number)
{
char i;
/* Null for now */
for (i=0; i<number; i++)
{
/* Clock out an idle byte (0xFF) */
spi_send_byte(0xFF);
}
}
//**********************************************************************************//
// Function Name: spi_send_data //
// Arguments : NONE //
// Return Types : NONE //
// Description : Function to transmit no of bytes to slave specified by //
// "U16 no_byte" argument & "U8 *data" is the source of bytes //
//**********************************************************************************//
void spi_send_data(U8 *data, U16 no_byte)
{
U8 temp_count;
if(no_byte > 0)
{
for(temp_count = 0; temp_count < no_byte; temp_count++)
{
spi_send_byte(*data);
data++;
}
}
}
UBYTE sd_cmd58()
{
BYTE r;
sd_wait_ready();
spi_send_byte(0x7a);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0xff);
r = sd_wait_r1();
spi_delay(); // if &0xc0==0xc0 => SDHC
spi_delay();
spi_delay();
spi_delay();
#ifdef DEBUG_SD
debug_puts("cmd58:");
debug_print_byte(r);
debug_puts("\n");
#endif
return r;
}
UBYTE sd_cmd8()
{
BYTE r;
sd_wait_ready();
spi_send_byte(0x48);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x01);
spi_send_byte(0xaa);
spi_send_byte(0x87);
r = sd_wait_r1();
spi_delay();
spi_delay();
spi_delay();
spi_delay();
spi_delay();
#ifdef DEBUG_SD
debug_puts("cmd8:");
debug_print_byte(r);
debug_puts("\n");
#endif
return r;
}
static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
{
unsigned int val;
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev | 1); /* READ */
val = spi_read_byte(ice);
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
return val;
}
static int write_data (
uint8 *buff, /* 512 byte data block to be transmitted */
uint8 token /* Data/Stop token */
)
{
uint8 resp;
uint16 crc;
int old;
if (wait_ready() != 0xFF)
return -1;
spi_send_byte(token); /* Xmit data token */
if (token != 0xFD) { /* Is data token */
dcache_pref_range((uint32)buff, 512);
crc = net_crc16ccitt(buff, 512, 0);
old = irq_disable();
spi_send_data(buff, 512);
spi_send_byte((uint8)(crc >> 8));
spi_send_byte((uint8)crc);
irq_restore(old);
resp = spi_rec_byte(); /* Reсeive data response */
if ((resp & 0x1F) != 0x05) { /* If not accepted, return with error */
#ifdef SD_DEBUG
dbglog(DBG_DEBUG, "%s: not accepted: %02x\n", __func__, resp);
#endif
errno = EIO;
return -1;
}
}
/* get data from iqrf */
uint8_t iqrf_get_data(uint8_t len)
{
uint8_t crcs ;
ptype = 0x00+len;
/* crc slave */
crcs = ptype ^ 0x5F;
/* crc master */
crcm = 0xF0 ^ ptype ^ 0x5F;
spi_send_byte(0xF0);
spi_send_byte(ptype);
for (i = 0; i < len; i++) {
iqrfRx[i] = spi_transcieve_byte(0x00);
crcs ^= iqrfRx[i];
}
iqrfRx[len] = spi_transcieve_byte(crcm);
if (crcs == iqrfRx[len]) {
fRxIQRF = len;
temp = 1;
} else {
temp = 0;
}
/* according spec. some dummy bytes */
spi_send_byte(0x00);
spi_send_byte(0x00);
return temp;
}
uint8_t iqrf_status(void)
{
uint8_t status;
status = spi_transcieve_byte(0x00);
printf("stat=%x\n", status);
switch (status) {
case 0x00: /* SPI disabled SW */
case 0x07: /* SPI disabled HW*/
case 0xFF: /* HW chyba */
case 0x81: /* programming mode */
case 0x82: /* debug mode */
return 0;
break;
case 0x83: /* slow mode - add delay */
slowModeDelay = 200;
return 1;
break;
case 0x80: /* SPI ready */
slowModeDelay = 0;
return 1;
break;
case 0x3E: /* full buff CRC ERR */
IQRF_ErrCount++;
case 0x3F: /* full buff CRC ok */
spi_send_byte(0x00);
return 0;
break;
/* data available */
default:
status -= 0x40;
if ((status > 0) && (status < 42))
iqrf_get_data(status);
return 0;
}
return 0;
}
static uint8 send_cmd (
uint8 cmd, /* Command byte */
uint32 arg /* Argument */
)
{
uint8 n, res;
uint8 cb[6];
if (wait_ready() != 0xFF) {
#ifdef SD_DEBUG
dbglog(DBG_DEBUG, "%s: CMD 0x%02x wait ready error\n", __func__, cmd);
#endif
return 0xFF;
}
cb[0] = cmd;
cb[1] = (uint8)(arg >> 24);
cb[2] = (uint8)(arg >> 16);
cb[3] = (uint8)(arg >> 8);
cb[4] = (uint8)arg;
cb[5] = sd_crc7(cb, 5, 0);
/* Send command packet */
int old = irq_disable();
spi_send_byte(cmd); /* Command */
spi_send_byte(cb[1]); /* Argument[31..24] */
spi_send_byte(cb[2]); /* Argument[23..16] */
spi_send_byte(cb[3]); /* Argument[15..8] */
spi_send_byte(cb[4]); /* Argument[7..0] */
spi_send_byte(cb[5]); // CRC7
/* Receive command response */
if (cmd == CMD12)
(void)spi_rec_byte(); /* Skip a stuff byte when stop reading */
n = 20; /* Wait for a valid response in timeout of 10 attempts */
do {
res = spi_rec_byte();
} while ((res & 0x80) && --n);
#ifdef SD_DEBUG
dbglog(DBG_DEBUG, "%s: CMD 0x%02x response 0x%02x\n", __func__, cmd, res);
#endif
irq_restore(old);
return res; /* Return with the response value */
}
UBYTE sd_cmd0()
{
BYTE r;
sd_wait_ready();
spi_send_byte(0x40);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x95);
r = sd_wait_r1();
#ifdef DEBUG_SD
debug_puts("cmd0:");
debug_print_byte(r);
debug_puts("\n");
#endif
return r;
}
UBYTE sd_acmd41(UBYTE byte0)
{
BYTE r;
spi_send_byte(0x77); // CMD55
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0xff);
r = sd_wait_r1();
if (r>1) {
#ifdef DEBUG_SD
debug_puts("cmd55 failed:");
debug_print_byte(r);
debug_puts("\n");
#endif
return -1;
}
sd_wait_ready();
spi_send_byte(0x69); // CMD41
spi_send_byte(byte0);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0x00);
spi_send_byte(0xff);
r = sd_wait_r1();
#ifdef DEBUG_SD
debug_puts("acmd41:");
debug_print_byte(r);
debug_puts("\n");
#endif
return r;
}
void ledmatrix_clear(void) {
(void)spi_send_byte(CMD_CLEAR_SCREEN);
}
/**
* \ingroup sd_raw
* Writes raw data to the card.
*
* \note If write buffering is enabled, you might have to
* call sd_raw_sync() before disconnecting the card
* to ensure all remaining data has been written.
*
* \param[in] offset The offset where to start writing.
* \param[in] buffer The buffer containing the data to be written.
* \param[in] length The number of bytes to write.
* \returns 0 on failure, 1 on success.
* \see sd_raw_write_interval, sd_raw_read, sd_raw_read_interval
*/
uint8_t sd_raw_write(uint32_t offset, const uint8_t* buffer, uint16_t length)
{
#if SD_RAW_WRITE_SUPPORT
if(get_pin_locked())
return 0;
uint32_t block_address;
uint16_t block_offset;
uint16_t write_length;
while(length > 0)
{
/* determine byte count to write at once */
block_address = offset & 0xfffffe00;
block_offset = offset & 0x01ff;
write_length = 512 - block_offset; /* write up to block border */
if(write_length > length)
write_length = length;
/* Merge the data to write with the content of the block.
* Use the cached block if available.
*/
if(block_address != raw_block_address)
{
#if SD_RAW_WRITE_BUFFERING
if(!sd_raw_sync())
return 0;
#endif
if(block_offset || write_length < 512)
{
if(!sd_raw_read(block_address, raw_block, sizeof(raw_block)))
return 0;
}
raw_block_address = block_address;
}
if(buffer != raw_block)
{
memcpy(raw_block + block_offset, buffer, write_length);
#if SD_RAW_WRITE_BUFFERING
raw_block_written = 0;
if(length == write_length)
return 1;
#endif
}
/* address card */
select_card();
/* send single block request */
if(sd_raw_send_command_r1(CMD_WRITE_SINGLE_BLOCK, block_address))
{
unselect_card();
spi_rec_byte();
return 0;
}
/* send start byte */
spi_send_byte(0xfe);
/* write byte block */
spi_send_data(raw_block, 512);
/* write dummy crc16 */
spi_send_byte(0xff);
spi_send_byte(0xff);
/* wait while card is busy */
/*
uint16_t i;
for(i = 0; i < 0x7fff; ++i)
{
if(spi_rec_byte() == 0xff)
break;
}
if(i >= 0x7fff)
{
unselect_card();
spi_rec_byte();
return 0;
}
*/
// obiger code reicht bei langsamen Karten nicht aus!
// daher nachfolgende alte Version mit endlos Warteschleife
// Wil.
while(spi_rec_byte() != 0xff);
spi_rec_byte();
/* deaddress card */
unselect_card();
buffer += write_length;
offset += write_length;
length -= write_length;
#if SD_RAW_WRITE_BUFFERING
raw_block_written = 1;
#endif
}
return 1;
#else
return 0;
#endif
}
void ledmatrix_update_pixel(uint8_t x, uint8_t y, PixelColour pixel) {
(void)spi_send_byte(CMD_UPDATE_PIXEL);
(void)spi_send_byte( ((y & 0x07)<<4) | (x & 0x0F));
(void)spi_send_byte(pixel);
}
void ledmatrix_shift_display_down(void) {
(void)spi_send_byte(CMD_SHIFT_DISPLAY);
(void)spi_send_byte(0x04);
}
void spi_delay()
{
spi_send_byte(0xff);
}
void ledmatrix_shift_display_right(void) {
(void)spi_send_byte(CMD_SHIFT_DISPLAY);
(void)spi_send_byte(0x01);
}
int sd_init()
{
UBYTE timeout;
spi_set_speed(0x7f); // min speed
// wait a bit
spi_assert_cs();
for(timeout=0x10; timeout>0; --timeout) {
spi_send_byte(0xff);
}
spi_deassert_cs();
spi_send_byte(0xff);
spi_send_byte(0xff);
spi_assert_cs();
// go into idle state
timeout = 0xff;
while (sd_cmd0() != 0x01) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
if (sd_cmd8() == 0x01) {
// SD card V2+
#ifdef DEBUG_SD
debug_puts("SD card V2+\n");
#endif
// initialize card
timeout = 0xff;
while ((sd_acmd41(0x40)&1)!=0) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
// read OCR
if (sd_cmd58()!=0) {
spi_deassert_cs();
return FALSE;
}
} else {
// SD card V1 or MMC
if (sd_acmd41(0x00)<=1) {
// SD V1
#ifdef DEBUG_SD
debug_puts("SD V1\n");
#endif
timeout = 0xff;
while ((sd_acmd41(0x00)&1)!=0) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
} else {
// MM Card : fail
#ifdef DEBUG_SD
debug_puts("MMC\n");
#endif
spi_deassert_cs();
return FALSE;
}
}
spi_deassert_cs();
spi_set_speed(0x00); // max speed
return TRUE;
}
int sd_send_command(sd_context_t *sdc,
unsigned char cmd, unsigned char response_type,
unsigned char *response, unsigned char *argument)
{
int i;
char response_length;
unsigned char tmp;
spi_cs_assert();
/* All data is sent MSB first, and MSb first */
/* Send the header/command */
/* Format:
cmd[7:6] : 01
cmd[5:0] : command */
spi_send_byte((cmd & 0x3F) | 0x40);
for (i=3; i>=0; i--)
{
spi_send_byte(argument[i]);
}
/* This is the CRC. It only matters what we put here for the first
command. Otherwise, the CRC is ignored for SPI mode unless we
enable CRC checking. */
spi_send_byte(0x95);
response_length = 0;
switch (response_type)
{
case R1:
case R1B:
response_length = 1;
break;
case R2:
response_length = 2;
break;
case R3:
response_length = 5;
break;
default:
break;
}
/* Wait for a response. A response can be recognized by the
start bit (a zero) */
i=0;
do
{
tmp = spi_rcv_byte();
i++;
}
while (((tmp & 0x80) != 0) && i < SD_CMD_TIMEOUT);
/* Just bail if we never got a response */
if (i >= SD_CMD_TIMEOUT)
{
spi_cs_deassert();
return 0;
}
for (i=response_length-1; i>=0; i--)
{
response[i] = tmp;
/* This handles the trailing-byte requirement. */
tmp = spi_rcv_byte();
}
/* If the response is a "busy" type (R1B), then there's some
* special handling that needs to be done. The card will
* output a continuous stream of zeros, so the end of the BUSY
* state is signaled by any nonzero response. The bus idles
* high.
*/
i=0;
if (response_type == R1B)
{
do
{
i++;
tmp = spi_rcv_byte();
}
/* This should never time out, unless SDI is grounded.
* Don't bother forcing a timeout condition here. */
while (tmp != 0xFF);
spi_send_byte(0xFF);
}
spi_cs_deassert();
return 1;
}
int sd_read_block (sd_context_t *sdc, u32 blockaddr, unsigned char *data){
unsigned long int i = 0;
unsigned char tmp;
unsigned char blank = 0xFF;
blockaddr <<= SD_BLOCKSIZE_NBITS; //Adjust the block address to a linear address.
sd_wait_notbusy (sdc); //Wait until any old transfers are finished.
sd_packarg(argument, blockaddr); //Pack the address.
if (sd_send_command(sdc, CMD17, CMD17_R, response, argument) == 0){ //Need to add size checking.
return 0;
}
if (response[0] != 0){ // Check for an error, like a misaligned read.
return 0;
}
spi_cs_assert(); //Re-assert CS to continue the transfer.
i=0; //Wait for the token.
do{
tmp = spi_rcv_byte();
i++;
}
while ((tmp == 0xFF) && i < sdc->timeout_read );
if ((tmp & MSK_TOK_DATAERROR) == 0){ //Clock out a byte before returning.
spi_send_byte(0xFF); //The card returned an error response. Bail and return 0
return 0;
}
//----------------------------------Prime the interrupt flags so things happen in the correct order.------------------------------------
IFG1 &= ~URXIFG0;
IFG1 &= ~UTXIFG0;
/* Get the block */
/* Source DMA address: receive register. */
DMA0SA = U0RXBUF_;
/* Destination DMA address: the user data buffer. */
DMA0DA = (unsigned short)data;
/* The size of the block to be transferred */
DMA0SZ = SD_BLOCKSIZE;
/* Configure the DMA transfer*/
DMA0CTL =
DMADT_0 | /* Single transfer mode */
DMASBDB | /* Byte mode */
DMAEN | /* Enable DMA */
DMADSTINCR1 | DMADSTINCR0; /* Increment the destination address */
/* We depend on the DMA priorities here. Both triggers occur at
the same time, since the source is identical. DMA0 is handled
first, and retrieves the byte. DMA1 is triggered next, and
sends the next byte. */
/* Source DMA address: constant 0xFF (don’t increment)*/
DMA1SA = (unsigned short)␣ /* Destination DMA address: the transmit buffer. */
DMA1DA = U0TXBUF_; /* Increment the destination address */
DMA1SZ = SD_BLOCKSIZE-1; /* The size of the block to be transferred */
DMA1CTL = /* Configure the DMA transfer*/
DMADT_0 | /* Single transfer mode */
DMASBDB | /* Byte mode */
DMAEN; /* Enable DMA */
DMACTL0 = DMA0TSEL_3 | DMA1TSEL_3; /* DMA trigger is UART receive for both DMA0 and DMA1 */
U0TXBUF = 0xFF; /* Kick off the transfer by sending the first byte */
return 1;
}
