int sd_ver(void) {
int ver;
spi_sendbyte(0x48); //index command cmd8
spi_sendbyte(0x00); //first arg's byte
spi_sendbyte(0x00); //2-nd arg's byte
spi_sendbyte(0x01); //3-rd arg's byte
spi_sendbyte(0xAA); //4-th arg's byte
spi_sendbyte(0X00); // CRC
do {
status_=spi_sendbyte(0xFF);
// SD v.1
if (status_==0x04 || status_==0x05) {
ver = 1;
}
// SD v.2
if (status_==0x01) {
ver = 2;
}
} while((status_!=0x01) && (status_!=0x04) && (status_!=0x05));
return ver;
}
void writeregs ( uint8_t data[] , uint8_t size )
{
spi_cson();
for ( uint8_t i = 0 ; i < size ; i++)
{
spi_sendbyte( data[i]);
}
spi_csoff();
delay(1000);
}
unsigned char * sd_read(unsigned long int bpos) {
CS_LOW();
spi_sendbyte(0xFF);
//converting bpos to 4 bytes and set read-start position
spi_sendbyte(0x51);
spi_sendbyte(((bpos & 0xFF000000)>>24));
spi_sendbyte(((bpos & 0x00FF0000)>>16));
spi_sendbyte(((bpos & 0x0000FF00)>>8));
spi_sendbyte(((bpos & 0x000000FF)));
spi_sendbyte(0x00); //CRC
while (spi_sendbyte(0xFF)!=0x0);
while (spi_sendbyte(0xFF)!=0xFE); //waiting for byte of the transmission start signal
for (int i=0; i<SIG_LEN; i++) {
ret_sig[i] = spi_sendbyte(0xFF);
}
for (int i=0; i<(512-SIG_LEN); i++) {
spi_sendbyte(0xFF);
}
spi_sendbyte(0x00); //1-st byte CRC
spi_sendbyte(0x00); //2-nd byte CRC
CS_HIGH();
test(2);
return ret_sig;
}
void sd2spi(void) {
CS_HIGH();
for (int i = 0; i < 10; i++) {
spi_sendbyte(0xFF);
}
CS_LOW();
//command CDM0
spi_sendbyte(0x40); //index command cmd0
spi_sendbyte(0x00); //first arg's byte
spi_sendbyte(0x00); //2-nd arg's byte
spi_sendbyte(0x00); //3-rd arg's byte
spi_sendbyte(0x00); //4-th arg's byte
spi_sendbyte(0x95); // CRC
while ((status_=spi_sendbyte(0xFF))!=0x01);
test(4);
}
void sd_init(void) {
CS_LOW();
while (1) {
spi_sendbyte(0x41); //CMD1
spi_sendbyte(0x00);
spi_sendbyte(0x00);
spi_sendbyte(0x00);
spi_sendbyte(0x00);
spi_sendbyte(0xFF);
spi_sendbyte(0xFF); //byte waiting
status_=spi_sendbyte(0xFF); //check status
if (status_ != 0xFF) {
if (status_ == 0x0) break;
}
}
CS_HIGH();
}
void spi_off(void){
SPCR &= ~(1<<CPOL);
spi_sendbyte(0x00);
spi_sendbyte(0x00);
_delay_us(10);
}
void spi_on(void){
SPCR |= (1<<CPOL);
spi_sendbyte(0x00);
spi_sendbyte(0x00);
_delay_us(10);
}
void spi_sendarray(uint8_t *array, uint8_t length){
uint8_t i =0;
for(i =0; i<length; i++){
spi_sendbyte(*(array+i));
}
}
void sd_write(char __flash *str, unsigned long int bpos) {
CS_LOW();
spi_sendbyte(0xFF);
//converting bpos to 4 bytes and set write-start position
spi_sendbyte(0x58);
spi_sendbyte(((bpos & 0xFF000000)>>24));
spi_sendbyte(((bpos & 0x00FF0000)>>16));
spi_sendbyte(((bpos & 0x0000FF00)>>8));
spi_sendbyte(((bpos & 0x000000FF)));
spi_sendbyte(0x00); //CRC
while (spi_sendbyte(0xFF)!=0x0);
spi_sendbyte(0xFF);
spi_sendbyte(0xFE);
_spi_sendtext(str); //str len up to 512 bytes
spi_sendbyte(0x00); //1-st byte CRC
spi_sendbyte(0x00); //2-nd byte CRC
while (spi_sendbyte(0xFF)&0x5 != 0x5); //waiting for the command reception signal
while (spi_sendbyte(0xFF)!=0x00); //waiting for the command reception signal
test(2);
CS_HIGH();
}
void _spi_sendtext(char __flash *str) {
int i = 0;
while (str[i]) {
spi_sendbyte(str[i++]);
}
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
#define XN_POWER B00000111
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
// set above
// xn_writereg( 29 , 32); // feture reg , CE mode (software controlled)
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
void check_radio(void);
check_radio();
#endif
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef AUX4_START_ON
aux[CH_AUX4] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
//static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , B00100111 , B00000000};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
//#define XN_POWER B00000111 // disabled by silverAG for SilverVISE - value is added from config.h
// SilverVISE - start:
#ifdef TX_POWER_GENERAL
// use value from config.h
#define XN_POWER TX_POWER_GENERAL
#else
#define XN_POWER B00000111
#endif
// SilverVISE - end
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
int rxcheck = xn_readreg( 0x0f); // rx address pipe 5
// should be 0xc6
extern void failloop( int);
if ( rxcheck != 0xc6) failloop(3);
#endif
}
