void spi_setup(void) {
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
/* For spi signal pins */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPAEN);
/* For spi mode select on the l3gd20 */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPEEN);
/* Setup GPIOE3 pin for spi mode l3gd20 select. */
gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Start with spi communication disabled */
gpio_set(GPIOE, GPIO3);
/* Setup GPIO pins for AF5 for SPI1 signals. */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
//spi initialization;
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_full_duplex_mode(SPI1);
spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_8BIT);
spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_high(SPI1);
//spi_enable_ss_output(SPI1);
spi_fifo_reception_threshold_8bit(SPI1);
SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
/**
* \internal
* \brief Initialize Proxy PLC controller.
*
* This function will change the system clock prescaler configuration to
* match the parameters.
*
* \note The parameters to this function are device-specific.
*
*/
static void _pplc_if_config(void)
{
uint32_t ul_cpuhz;
uint8_t uc_div;
ul_cpuhz = sysclk_get_cpu_hz();
uc_div = ul_cpuhz / gs_ul_pplc_clock;
/* Enable SPI peripheral. */
spi_enable_clock(PPLC_SPI_MODULE);
/* Reset SPI */
spi_disable(PPLC_SPI_MODULE);
spi_reset(PPLC_SPI_MODULE);
/* Configure SPI */
spi_set_master_mode(PPLC_SPI_MODULE);
spi_disable_mode_fault_detect(PPLC_SPI_MODULE);
spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS);
spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0);
spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1);
spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT);
spi_set_fixed_peripheral_select(PPLC_SPI_MODULE);
spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div);
spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS,
PPLC_DLYBCT);
spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX);
/* Get board PPLC PDC base address and enable receiver and transmitter */
g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE);
spi_enable(PPLC_SPI_MODULE);
}
//Setup hardware
TouchADS7843::TouchADS7843(void)
{
//Enable clocks
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN); //SPI
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); //SPI
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); //PEN_INT
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); //AFIO (EXTI)
//Setup GPIO
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, BIT13); //PEN_INT
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, BIT6); //MISO
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, BIT4); //CS
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, BIT5 | BIT7); //MOSI, SCK
//Set up SPI as mater
_cs(1);
spi_enable_software_slave_management(SPI1);
spi_set_nss_high(SPI1);
spi_set_baudrate_prescaler(SPI1, 7);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_dff_8bit(SPI1);
spi_set_master_mode(SPI1);
spi_enable(SPI1);
//Enable PEN_INT
nvic_enable_irq(NVIC_EXTI15_10_IRQ);
exti_select_source(EXTI13, GPIOC);
exti_set_trigger(EXTI13, EXTI_TRIGGER_BOTH);
exti_reset_request(EXTI13);
exti_enable_request(EXTI13);
}
/* Setup the SPI bus. This function may cause spurious signals on the SPI bus,
* so it should be called before the transaction starts (i.e. while SS is high).
* -CPOL is the clock polarity (0 or 1)
* -CPHA is the clock phase (0 or 1)
* -baudrate is one of libopencm3's SPI_CR1_BAUDRATE_FPCLK_DIV_X values.
* Baudrates are derived from the low-speed peripheral clock APB1.
* -firstbit is either SPI_CR1_MSBFIRST or SPI_CR1_LSBFIRST. */
void setup_spi(uint8_t cpol, uint8_t cpha, uint8_t baudrate, uint8_t firstbit){
disable_and_reset_spi_properly();
SPI_CR1(SPI3) &= 0xFFC7; /* Mask off baudrate bits. */
SPI_CR1(SPI3) |= baudrate;
if(0 == cpol){
spi_set_clock_polarity_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
if(0 == cpha){
spi_set_clock_phase_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
spi_set_unidirectional_mode(SPI3); /* bidirectional but in 3-wire */
spi_set_full_duplex_mode(SPI3);
SPI_CR1(SPI3) &= ~SPI_CR1_LSBFIRST;
SPI_CR1(SPI3) |= firstbit;
spi_enable_software_slave_management(SPI3);
spi_set_nss_high(SPI3);
spi_set_master_mode(SPI3);
spi_set_data_size(SPI3, SPI_CR2_DS_8BIT);
spi_fifo_reception_threshold_8bit(SPI3);
SPI_I2SCFGR(SPI3) &= ~SPI_I2SCFGR_I2SMOD;
/* All DMA configuration is handled by tx_spi(), rx_spi(), and rxtx_spi(). */
}
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @param[in] miso The pin to use for MISO
* @param[in] sclk The pin to use for SCLK
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
MBED_ASSERT(obj);
MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
if (g_sys_init == 0) {
sysclk_init();
system_board_init();
g_sys_init = 1;
}
Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
MBED_ASSERT(sercombase!=NC);
pinmap_find_spi_info(sercombase, obj);
MBED_ASSERT(obj->spi.flexcom!=NC);
MBED_ASSERT(obj->spi.pdc!=NC);
/* Configure SPI pins */
pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
ioport_disable_pin(mosi);
pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
ioport_disable_pin(miso);
pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
ioport_disable_pin(sclk);
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(obj->spi.flexcom);
flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
spi_enable_clock(sercombase);
#endif
spi_disable(sercombase);
spi_reset(sercombase);
spi_set_lastxfer(sercombase);
spi_set_master_mode(sercombase);
spi_disable_mode_fault_detect(sercombase);
spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
spi_enable(sercombase);
pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
obj->spi.spi_base=sercombase;
obj->spi.cs= SPI_CHIP_SEL;
obj->spi.polarity=SPI_CLK_POLARITY;
obj->spi.phase=SPI_CLK_PHASE;
obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
obj->spi.is_slave=0;
}
void init_codec() {
/* enable clock for Aux power and power up the regulators */
rcc_peripheral_enable_clock(&CODEC_PWR_APB, CODEC_RCC_PWR);
gpio_set_mode(CODEC_PWR_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_PWR);
gpio_set(CODEC_PWR_PORT, CODEC_PWR);
/* enable SPI1 clock */
rcc_peripheral_enable_clock(&CODEC_SPI_APB, CODEC_RCC_SPI);
/* enable clock for the chip select pin */
rcc_peripheral_enable_clock(&CODEC_IOS_APB, CODEC_RCC_IOS);
/* enable clock for the RST/DREQ lines */
rcc_peripheral_enable_clock(&CODEC_IOI_APB, CODEC_RCC_IOI);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
/* set the pin modes for the SPI pins */
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_CS);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_MOSI);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_SCK);
gpio_set_mode(CODEC_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_MISO);
/* set the modes for the reset and busy pins */
gpio_set_mode(CODEC_RST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_RST);
gpio_set_mode(CODEC_DREQ_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_DREQ);
gpio_clear(CODEC_RST_PORT, CODEC_RST);
/* configure the SPI port */
spi_set_unidirectional_mode(CODEC_SPI);
spi_disable_crc(CODEC_SPI);
spi_set_dff_8bit(CODEC_SPI);
spi_set_full_duplex_mode(CODEC_SPI);
spi_enable_software_slave_management(CODEC_SPI);
spi_set_nss_high(CODEC_SPI);
spi_set_baudrate_prescaler(CODEC_SPI, SPI_CR1_BR_FPCLK_DIV_32);
spi_set_master_mode(CODEC_SPI);
spi_send_msb_first(CODEC_SPI);
spi_set_clock_polarity_0(CODEC_SPI);
spi_set_clock_phase_0(CODEC_SPI);
spi_disable_ss_output(CODEC_SPI);
spi_enable(CODEC_SPI);
/* disable chip select */
gpio_set(CODEC_PORT, CODEC_CS);
/* make sure reset is not asserted */
gpio_set(CODEC_RST_PORT, CODEC_RST);
return;
}
/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
spi_enable_clock(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register.
spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR).
spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device.
spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);
/* Set communication parameters for CS0 */
spi_chip_sel = 0;
spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed.
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS1 */
spi_chip_sel = 1;
spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz.
spi_clk_pol = 0;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS2 */
spi_chip_sel = 2;
spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Enable SPI Communication */
spi_enable(SPI_MASTER_BASE);
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
spi_enable_clock(p_spi);
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
static void _spi_init_base(Spi * spi_base)
{
spi_enable_clock(spi_base);
spi_disable(spi_base);
spi_reset(spi_base);
spi_set_lastxfer(spi_base);
spi_set_master_mode(spi_base);
spi_disable_mode_fault_detect(spi_base);
spi_set_variable_peripheral_select(spi_base);
spi_enable_interrupt(_spi_base, SPI_IER_RDRF);
// spi_enable_loopback(spi_base); // ??????????????????
}
/*
* @fn nm_bus_init
* @brief Initialize the bus wrapper
* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
*/
sint8 nm_bus_init(void *pvinit)
{
sint8 result = M2M_SUCCESS;
#ifdef CONF_WINC_USE_I2C
twihs_options_t opt;
/* Enable the peripheral clock for TWI */
pmc_enable_periph_clk(CONF_WINC_I2C_ID);
/* Configure the options of TWI driver */
opt.master_clk = sysclk_get_peripheral_hz();
opt.speed = CONF_WINC_TWIHS_CLOCK;
if (twihs_master_init(CONF_WINC_I2C, &opt) != TWIHS_SUCCESS) {
M2M_ERR("-E-\tTWI master initialization failed.\r");
while (1) {
/* Capture error */
}
}
#elif CONF_WINC_USE_SPI
/* Configure SPI pins. */
ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS);
ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO);
ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CS_GPIO);
spi_enable_clock(CONF_WINC_SPI);
spi_disable(CONF_WINC_SPI);
spi_reset(CONF_WINC_SPI);
spi_set_master_mode(CONF_WINC_SPI);
spi_disable_mode_fault_detect(CONF_WINC_SPI);
spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS);
spi_set_clock_polarity(CONF_WINC_SPI,
CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL);
spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA);
spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS,
(sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK));
spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS,
CONF_WINC_SPI_DLYBCT);
spi_enable(CONF_WINC_SPI);
nm_bsp_reset();
#endif
return result;
}
static int spi_set_params(struct s3c2410_spi *device)
{
spi_set_def_prescale(device);
spi_set_master_mode(device);
spi_set_clock_mode(device);
spi_enable_sck(device);
sppin_set_keep(0x1); /* stay in master mode after tx */
sppin_set_resv1(0x1); /* according to spec this should be 1 */
dprintf("%s: done\n", __func__);
return 0;
}
void spi_start(void)
{
/* Reset flash chip */
gpio_clear(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_WP);
/* No WriteProtect, Set Chip select to 1(no select) */
gpio_set(GPIOB, BL_SPI2_NSS);
/* Reset and disable SPI */
spi_reset(SPI2);
/* Disable I2S */
SPI2_I2SCFGR = 0;
/* CR1 */
spi_set_clock_phase_0(SPI2); /* CPHA = 0 */
spi_set_clock_polarity_0(SPI2); /* CPOL = 0 */
spi_send_msb_first(SPI2); /* LSB = 0 */
spi_set_full_duplex_mode(SPI2); /* RXONLY = 0 */
spi_set_unidirectional_mode(SPI2); /* BIDI = 0 */
spi_enable_software_slave_management(SPI2); /* SSM = 1 */
spi_set_nss_high(SPI2); /* SSI = 1 */
spi_set_master_mode(SPI2); /* MSTR = 1 */
spi_set_dff_8bit(SPI2); /* DFf = 8 bit */
// spi_enable_crc(SPI2);
/* XXX: Too fast? Maybe DIV_4 will be better? */
spi_set_baudrate_prescaler(SPI2, SPI_CR1_BR_FPCLK_DIV_2);
/* CR2 */
spi_enable_ss_output(SPI2); /* SSOE = 1 */
/* Disable regular interrupt flags */
spi_disable_tx_buffer_empty_interrupt(SPI2);
spi_disable_rx_buffer_not_empty_interrupt(SPI2);
spi_disable_error_interrupt(SPI2);
/* Enabling RX/TX DMA flags */
spi_enable_tx_dma(SPI2);
spi_enable_rx_dma(SPI2);
d_print("REG: %lu:%lu\r\n", SPI_CR1(SPI2), SPI_CR2(SPI2));
spi_enable(SPI2);
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
#if SAMG55
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
spi_enable_clock(p_spi);
#endif
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
static void spi_setup(void)
{
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_1(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_bidirectional_transmit_only_mode(SPI1);
//spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_16BIT);
//spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_low(SPI1);
//spi_enable_ss_output(SPI1);
//spi_fifo_reception_threshold_8bit(SPI1);
//SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
/**
* \brief Initialize SPI as master.
*/
static void radioSpiInit(void)
{
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
(sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
SPI_DLYBCT);
spi_enable(SPI_MASTER_BASE);
}
