u32 platform_spi_setup( spi_userdata *spi, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits ) {
if (spi_init(spi->spi) != 0) {
return 0;
}
spi_set_speed(spi->spi, spi->speed);
spi_set_cspin(spi->spi, spi->cs);
spi_deselect(spi->spi);
if (mode == 1) {
spi->mode = PIC32_SPICON_MSTEN | PIC32_SPICON_ON | PIC32_SPICON_CKE | PIC32_SPICON_SMP;
switch (databits) {
case 8:
break;
case 16:
spi->mode |= PIC32_SPICON_MODE16;
break;
case 32:
spi->mode |= PIC32_SPICON_MODE16;
break;
}
spi_set(spi->spi, spi->mode);
} else {
return 0;
}
return 0;
}
int cfi_init(int unit) {
struct cfi *cfi = &cfid[unit];
int spi;
if (inited) return 1;
switch (unit) {
case 0:
cfi->spi = CFI_SPI;
cfi->unit = 0;
cfi->cs = CFI_CS;
cfi->speed = CFI_KHZ;
break;
}
spi = cfi->spi;
// Init spi port
if (spi_init(spi) != 0) {
syslog(LOG_ERR, "cfi%u cannot open spi%u port", unit, spi);
return 0;
}
spi_set_cspin(spi, cfi->cs);
spi_set_speed(spi, cfi->speed);
spi_set(spi, PIC32_SPICON_CKE);
syslog(LOG_INFO,
"cfi%u is at port %s, pin cs=%c%d",
cfi->unit, spi_name(spi), spi_csname(spi), spi_cspin(spi)
);
// Setup driver
return cfi_setup(cfi);
}
static void mmc_spi_set_ios(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
debug("%s: clock %u\n", __func__, mmc->clock);
if (mmc->clock)
spi_set_speed(spi, mmc->clock);
}
static int mmc_spi_init_p(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
spi_claim_bus(spi);
/* cs deactivated for 100+ clock */
spi_xfer(spi, 18 * 8, NULL, NULL, 0);
spi_release_bus(spi);
return 0;
}
void platform_spi_select( spi_userdata *spi, int is_select ) {
spi_set_speed(spi->spi, spi->speed);
spi_clr_and_set(spi->spi, spi->mode);
if (is_select) {
spi_select(spi->spi);
} else {
spi_deselect(spi->spi);
}
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct bfin_spi_slave *bss;
u32 reg_base;
if (!spi_cs_is_valid(bus, cs))
return NULL;
if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
debug("%s: invalid bus %u\n", __func__, bus);
return NULL;
}
switch (bus) {
#ifdef SPI0_REGBASE
case 0:
reg_base = SPI0_REGBASE;
break;
#endif
#ifdef SPI1_REGBASE
case 1:
reg_base = SPI1_REGBASE;
break;
#endif
#ifdef SPI2_REGBASE
case 2:
reg_base = SPI2_REGBASE;
break;
#endif
default:
return NULL;
}
bss = malloc(sizeof(*bss));
if (!bss)
return NULL;
bss->slave.bus = bus;
bss->slave.cs = cs;
bss->regs = (struct bfin_spi_regs *)reg_base;
bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
if (mode & SPI_CPHA)
bss->control |= SPI_CTL_CPHA;
if (mode & SPI_CPOL)
bss->control |= SPI_CTL_CPOL;
if (mode & SPI_LSB_FIRST)
bss->control |= SPI_CTL_LSBF;
bss->control &= ~SPI_CTL_ASSEL;
bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
spi_set_speed(&bss->slave, max_hz);
return &bss->slave;
}
//检测24L01是否存在
//返回值:0，成功;1，失败
uint8_t NRF24L01_Check(void)
{
uint8_t buf[5]={0XA5,0XA5,0XA5,0XA5,0XA5};
uint8_t i;
spi_set_speed(SPI_BaudRatePrescaler_8); //spi速度为10.5Mhz（24L01的最大SPI时钟为10Mhz）
NRF24L01_Write_Buf(NRF_WRITE_REG+TX_ADDR,buf,5); //写入5个字节的地址.
NRF24L01_Read_Buf(TX_ADDR,buf,5); //读出写入的地址
for(i=0;i<5;i++){
if(buf[i]!=0XA5){
return 1;//检测24L01错误
}
}
return 0; //检测到24L01
}
//启动NRF24L01发送一次数据
//txbuf:待发送数据首地址
//返回值:发送完成状况
void NRF24L01_TxPacket(uint8_t *txbuf)
{
spi_set_speed(SPI_BaudRatePrescaler_8);//spi速度为10.5Mhz（24L01的最大SPI时钟为10Mhz）
while(1){
if(nrf_state == TX_OK){
break;
}
else if(nrf_state == MAX_TX){
printf("NRF24L01: 带到最大发送次数\r\n");
break;
}
}
nrf_state = SENDING_DATA;
NRF24L01_CE=0;
NRF24L01_Write_Buf(WR_TX_PLOAD,txbuf,TX_PLOAD_WIDTH);//写数据到TX BUF 32个字节
NRF24L01_CE=1;//启动发送
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct bfin_spi_slave *bss;
u32 mmr_base;
if (!spi_cs_is_valid(bus, cs))
return NULL;
if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
debug("%s: invalid bus %u\n", __func__, bus);
return NULL;
}
switch (bus) {
#ifdef SPI0_CTL
case 0: mmr_base = SPI0_CTL; break;
#endif
#ifdef SPI1_CTL
case 1: mmr_base = SPI1_CTL; break;
#endif
#ifdef SPI2_CTL
case 2: mmr_base = SPI2_CTL; break;
#endif
default: return NULL;
}
bss = malloc(sizeof(*bss));
if (!bss)
return NULL;
bss->slave.bus = bus;
bss->slave.cs = cs;
bss->mmr_base = (void *)mmr_base;
bss->ctl = SPE | MSTR | TDBR_CORE;
if (mode & SPI_CPHA) bss->ctl |= CPHA;
if (mode & SPI_CPOL) bss->ctl |= CPOL;
if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
spi_set_speed(&bss->slave, max_hz);
debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
return &bss->slave;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int hz, unsigned int mode)
{
struct tiny_spi_slave *tiny_spi;
if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, "tiny_spi"))
return NULL;
tiny_spi = spi_alloc_slave(struct tiny_spi_slave, bus, cs);
if (!tiny_spi)
return NULL;
tiny_spi->host = &tiny_spi_host_list[bus];
tiny_spi->mode = mode & (SPI_CPOL | SPI_CPHA);
tiny_spi->flg = mode & SPI_CS_HIGH ? 1 : 0;
spi_set_speed(&tiny_spi->slave, hz);
debug("%s: bus:%i cs:%i base:%lx\n", __func__,
bus, cs, tiny_spi->host->base);
return &tiny_spi->slave;
}
/**
* Initializes and enables the SPI module
*
* IN: void
* OUT: int - error code (FALSE if no error)
**/
int spi_enable(void)
{
// Check to make sure module is not in use
//if()
//{
// return ERR_BUS_BUSY;
//}
//else
//{
// Set SMCLK ~ 1.832MHz (Change this for faster?)
//BCSCTL1 |= XTS; // Use HF mode Y U NO NOT DO DIS
BCSCTL1 &= ~XT2OFF; // Ensure XT2CLK is active
BCSCTL2 |= SELS; // SMCLK = XT2CLK
BCSCTL2 &= ~(DIVS0 + DIVS1); // Ensure SMCLK = XT2CLK / 1
// Configure Port 3
P3SEL |= SPI_SIMO + SPI_SOMI + SPI_SCLK; // Pins used by SPI module
__spi_deassert_cs(); // Set -CS_SD high
P3DIR |= SPI_CS; // Make sure -CS_SD is output
// Recommended initalization procedure
U0CTL = SWRST; // Software reset USART0
U0CTL |= CHAR + SYNC + MM; // 8 bit characters, SPI Master mode
U0MCTL = 0x00; // Modulation control not used for SPI
spi_set_speed(spi_cur_div); // Set the clock speed
U0TCTL |= CKPH + SSEL1 + STC; // UCLK delayed half cycle, UCLK = SMCLK/U0BRx, 3 pin
// Make sure Interrupts are cleared and disabled
IE1 &= ~(UTXIE0 + URXIE0);
IFG1 &= ~(UTXIFG0 + URXIFG0);
// Enable the SPI Module
ME1 |= USPIE0; // Enable the SPI module
U0CTL &= ~SWRST; // Clear SWRST
return NO_ERROR;
//}
}
int sd_init()
{
UBYTE timeout;
spi_set_speed(0x7f); // min speed
// wait a bit
spi_assert_cs();
for(timeout=0x10; timeout>0; --timeout) {
spi_send_byte(0xff);
}
spi_deassert_cs();
spi_send_byte(0xff);
spi_send_byte(0xff);
spi_assert_cs();
// go into idle state
timeout = 0xff;
while (sd_cmd0() != 0x01) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
if (sd_cmd8() == 0x01) {
// SD card V2+
#ifdef DEBUG_SD
debug_puts("SD card V2+\n");
#endif
// initialize card
timeout = 0xff;
while ((sd_acmd41(0x40)&1)!=0) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
// read OCR
if (sd_cmd58()!=0) {
spi_deassert_cs();
return FALSE;
}
} else {
// SD card V1 or MMC
if (sd_acmd41(0x00)<=1) {
// SD V1
#ifdef DEBUG_SD
debug_puts("SD V1\n");
#endif
timeout = 0xff;
while ((sd_acmd41(0x00)&1)!=0) {
if (timeout==0) {
spi_deassert_cs();
return FALSE;
}
timeout = timeout-1;
}
} else {
// MM Card : fail
#ifdef DEBUG_SD
debug_puts("MMC\n");
#endif
spi_deassert_cs();
return FALSE;
}
}
spi_deassert_cs();
spi_set_speed(0x00); // max speed
return TRUE;
}
static void spi_init(void)
{
/* Configure spi using CubeMX!!! */
spi_set_speed(SD_SPEED_400KHZ);
}
