void SPI_Read_ADXL(uint8_t* data)
{
port_pin_set_output_level(PIN_PA06, 0);
//spi_read_buffer_wait(&spi_master_instance_ADXL, data, 2, 0);
spi_transceive_buffer_wait(&spi_master_instance_ADXL, data, data, 2);
port_pin_set_output_level(PIN_PA06, 1);
}
void SPI_Read_AD5421(uint8_t* data)
{
port_pin_set_output_level(PIN_PA18, 0);
//spi_read_buffer_wait(&spi_master_instance_AD5421, data, 3, 0);
spi_transceive_buffer_wait(&spi_master_instance_AD5421, data, data, 3);
port_pin_set_output_level(PIN_PA18, 1);
}
/**
* \brief Write a register value.
*
* \param reg the register address to modify.
* \param wrdata the new register value.
*/
void ksz8851_reg_write(uint16_t reg, uint16_t wrdata)
{
uint8_t inbuf[4];
uint8_t outbuf[4];
uint16_t cmd = 0;
spi_select_slave(&ksz8851snl_master, &ksz8851snl_slave, true);
/* Move register address to cmd bits 9-2, make 32-bit address. */
cmd = (reg << 2) & REG_ADDR_MASK;
/* Last 2 bits still under "don't care bits" handled with byte enable. */
/* Select byte enable for command. */
if (reg & 2) {
/* Odd word address writes bytes 2 and 3 */
cmd |= (0xc << 10);
} else {
/* Even word address write bytes 0 and 1 */
cmd |= (0x3 << 10);
}
/* Add command write code. */
cmd |= CMD_WRITE;
outbuf[0] = cmd >> 8;
outbuf[1] = cmd & 0xff;
outbuf[2] = wrdata & 0xff;
outbuf[3] = wrdata >> 8;
/* Perform SPI transfer. */
spi_transceive_buffer_wait(&ksz8851snl_master, outbuf, inbuf, 4);
spi_select_slave(&ksz8851snl_master, &ksz8851snl_slave, false);
}
/**
* \internal
* \brief Test: Send & receive data using transceive functions.
*
* This test sends (writes) an array of data to the slave and
* receives (reads) the buffer back using transceive functions
* and compares.
*
* \param test Current test case.
*/
static void run_transceive_buffer_test(const struct test_case *test)
{
enum status_code status = STATUS_ERR_IO;
/* Skip test if initialization failed */
test_assert_true(test, spi_init_success,
"Skipping test due to failed initialization");
/* Start the test */
spi_transceive_buffer_job(&slave, slave_tx_buf, slave_rx_buf,
BUFFER_LENGTH);
spi_select_slave(&master, &slave_inst, true);
status = spi_transceive_buffer_wait(&master, tx_buf, rx_buf,
BUFFER_LENGTH);
spi_select_slave(&master, &slave_inst, false);
test_assert_true(test, status == STATUS_OK,
"Transceive buffer failed");
/* Compare received data with transmitted data */
if (status == STATUS_OK) {
for (uint16_t i = 0; i < BUFFER_LENGTH; i++) {
test_assert_true(test, tx_buf[i] == slave_rx_buf[i],
"During TX: Bytes differ at buffer index %d : %d != %d",
i, tx_buf[i], slave_rx_buf[i]);
test_assert_true(test, slave_tx_buf[i] == rx_buf[i],
"During RX: Bytes differ at buffer index %d : %d != %d",
i, slave_tx_buf[i], rx_buf[i]);
}
}
}
/**
* \brief Read internal fifo buffer.
*
* \param buf the buffer to store the data from the fifo buffer.
* \param len the amount of data to read.
*/
void ksz8851_fifo_read(uint8_t *buf, uint32_t len)
{
uint8_t tmpbuf[9];
spi_select_slave(&ksz8851snl_master, &ksz8851snl_slave, true);
tmpbuf[0] = FIFO_READ;
/* Perform SPI transfer. */
spi_transceive_buffer_wait(&ksz8851snl_master, tmpbuf, tmpbuf, 9);
spi_read_buffer_wait(&ksz8851snl_master, buf, len, 0xff);
/* Read CRC (don't care). */
spi_read_buffer_wait(&ksz8851snl_master, tmpbuf, 4, 0xff);
len += 4;
/* Keep internal memory alignment. */
len &= 3;
if (len) {
spi_read_buffer_wait(&ksz8851snl_master, tmpbuf, len, 0xff);
}
spi_select_slave(&ksz8851snl_master, &ksz8851snl_slave, false);
}
/**
* \brief Sends and reads data byte on SPI
*
* \param[in] data Data byte to send
* \param[in] tx_data SPI character to transmit
* \param[out] rx_data Pointer to store the received SPI character
*/
static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_t length)
{
spi_transceive_buffer_wait(&edbg_spi, tx_data, rx_data, length);
}
