static void spm_trigger_wfi_for_dpidle(struct pwr_ctrl *pwrctrl)
{
//sync_hw_gating_value(); /* for Vcore DVFS */
#if 0 //deepidle no need, vproc(ext buck) can't set to 0v, because SRAM perpheral control from vproc
spm_i2c_control(mt6333_BUSNUM, 1);
#endif
if (is_cpu_pdn(pwrctrl->pcm_flags)) {
mt_cpu_dormant(CPU_DEEPIDLE_MODE);
} else {
wfi_with_sync();
}
#if 0 //deepidle no need, vproc(ext buck) can't set to 0v, because SRAM perpheral control from vproc
spm_i2c_control(mt6333_BUSNUM, 0); /* restore I2C1 power */
#endif
}
static void spm_suspend_pre_process(struct pwr_ctrl *pwrctrl)
{
/* set PMIC WRAP table for suspend power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_SUSPEND);
// FIXME: wait for dual-vcore suspend test finish.
#if 1
if (is_dualvcore_pdn(pwrctrl->pcm_flags))
{
/* set LTE pd mode to avoid LTE power on after dual-vcore resume */
//spm_write(AP_PLL_CON7, spm_read(AP_PLL_CON7) | 0xF); // set before dual-vcore suspend
mt_cpufreq_apply_pmic_cmd(IDX_SP_VCORE_PDN_EN_HW_MODE); // if dual-vcore suspend enable, set VCORE_PND_EN to HW mode
//mt6331_upmu_set_rg_int_en_chrdet(0); // disable charger detection to avoid abnormal EINT.
//mt6331_upmu_set_rg_int_en_rtc(0); // mask rtc to avoid abnormal EINT.
}
else
#endif
mt_cpufreq_apply_pmic_cmd(IDX_SP_VCORE_PDN_EN_SW_MODE); // if dual-vcore suspend disable, set VCORE_PND_EN to SW mode
spm_i2c_control(I2C_CHANNEL, 1);
}
/*
static bool spm_set_suspend_pcm_ver(u32 *suspend_flags)
{
u32 flag;
flag = *suspend_flags;
if(mt_get_clk_mem_sel()==MEMPLL3PLL)
{
__spm_suspend.pcmdesc = &suspend_pcm_3pll;
flag |= SPM_VCORE_DVS_DIS;
}
else if(mt_get_clk_mem_sel()==MEMPLL1PLL)
{
__spm_suspend.pcmdesc = &suspend_pcm_1pll;
flag &= ~SPM_VCORE_DVS_DIS;
}
else
return false;
*suspend_flags = flag;
return true;
}
*/
static void spm_suspend_pre_process(struct pwr_ctrl *pwrctrl)
{
#if 0
u32 rdata1 = 0, rdata2 = 0;
#endif
/* set PMIC WRAP table for suspend power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_SUSPEND);
spm_i2c_control(I2C_CHANNEL, 1);
#if 0
/* for infra pdn (emi driving) */
spm_write(0xF0004000, spm_read(0xF0004000) | (1 << 24));
/* MEMPLL control for SPM */
spm_write(0xF000F5C8, 0x3010F030);
spm_write(0xF000F5CC, 0x50101010);
#endif
//spm_write(0xF0001070 , spm_read(0xF0001070) | (1 << 21)); // 26:26 enable
//spm_write(0xF0000204 , spm_read(0xF0000204) | (1 << 0)); // BUS 26MHz enable
//spm_write(0xF0001108 , 0x0);
#ifdef CONFIG_MD32_SUPPORT
//spm_write(MD32_BASE+0x2C, (spm_read(MD32_BASE+0x2C) & ~0xFFFF) | 0xcafe);
#endif
#if 0
pwrap_read(0x2c2, &rdata1);
pwrap_write(0x2c2, 0x0123);
pwrap_read(0x2c2, &rdata2);
if(rdata2 != 0x0123)
{
spm_crit2("suspend pmic wrapper 0x2c2, rdata1 = 0x%x, rdata2 = 0x%x\n", rdata1, rdata2);
BUG();
}
#endif
}
static void spm_suspend_post_process(struct pwr_ctrl *pwrctrl)
{
// FIXME: wait for dual-vcore suspend test finish.
#if 1
if (is_dualvcore_pdn(pwrctrl->pcm_flags))
{
/* restore LTE pd mode after dual-vcore resume */
//spm_write(AP_PLL_CON7, spm_read(AP_PLL_CON7) & ~0xF); // set after dual-vcore resume
/* enable charger detection */
//mt6331_upmu_set_rg_int_en_chrdet(1);
/* enable rtc */
//mt6331_upmu_set_rg_int_en_rtc(1);
/* set VCORE_PND_EN to SW mode */
mt_cpufreq_apply_pmic_cmd(IDX_SP_VCORE_PDN_EN_SW_MODE);
}
#endif
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
spm_i2c_control(I2C_CHANNEL, 0);
}
static void spm_suspend_post_process(struct pwr_ctrl *pwrctrl)
{
#if 0
u32 rdata1 = 0, rdata2 = 0;
pwrap_read(0x2c2, &rdata1);
pwrap_write(0x2c2, 0x3210);
pwrap_read(0x2c2, &rdata2);
if(rdata2 != 0x3210)
{
spm_crit2("resume pmic wrapper 0x2c2, rdata1 = 0x%x, rdata2 = 0x%x\n", rdata1, rdata2);
BUG();
}
#endif
#ifdef CONFIG_MD32_SUPPORT
//spm_write(MD32_BASE+0x2C, spm_read(MD32_BASE+0x2C) & ~0xFFFF);
#endif
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
spm_i2c_control(I2C_CHANNEL, 0);
}
