/* Function: mdlOutputs =======================================================
* Abstract:
*
* y0 = u * 0.1
* y1 = u * 0.2
* y2 = u * 0.3
* y3 = u * 0.4
* y4 = u * 0.5
* y5 = u * 0.6
*/
static void mdlOutputs(SimStruct *S, int_T tid)
{
InputRealPtrsType uPtrs = ssGetInputPortRealSignalPtrs(S,0);
boolean_T u0IsComplex = ssGetInputPortComplexSignal(S, 0) == COMPLEX_YES;
int_T iWidth = ssGetInputPortWidth(S, 0);
int_T i, j;
real_T gain = 0.0;
for (j=0; j<6; j++) {
real_T *y = ssGetOutputPortRealSignal(S,j);
/* Output of jth Port is gain [(j+1)*(0.1)] */
if (j != 2) {
gain += 0.1;
} else {
/* special case due to normalize numerical precision */
gain = 0.3;
}
for (i=0; i<iWidth; i++) {
*y++ = uPtrs[i][0] * gain;
if (u0IsComplex) {
*y++ = uPtrs[i][1] * gain;
}
}
}
}
static void mdlSetInputPortComplexSignal(SimStruct *S,
int_T port,
int_T iPortComplexSignal)
{
int_T oPortComplexSignal = ssGetOutputPortComplexSignal(S,0);
/* Set the complex signal of the input ports */
ssSetInputPortComplexSignal(S, port, iPortComplexSignal);
if(iPortComplexSignal == COMPLEX_YES){
/* Output port must be a complex signal */
if(oPortComplexSignal == COMPLEX_INHERITED){
ssSetOutputPortComplexSignal(S, 0, COMPLEX_YES);
}else if(oPortComplexSignal == COMPLEX_NO){
ssSetErrorStatus(S, "Output port must be complex.");
}
}else if(oPortComplexSignal != COMPLEX_NO){
/*
* The current input port is a real signal. If the other input port
* is a real signal, the output port must be a real signal.
*/
int_T otherPort = (port == 0)? 1 : 0;
int_T otherPortComplexSignal =
ssGetInputPortComplexSignal(S, otherPort);
if(otherPortComplexSignal == COMPLEX_NO){
/* Both input ports are real signals */
if(oPortComplexSignal == COMPLEX_INHERITED){
ssSetOutputPortComplexSignal(S, 0, COMPLEX_NO);
}else if(oPortComplexSignal == COMPLEX_YES){
ssSetErrorStatus(S, "Output port must be real.");
}
}
}
}
/* Function: propPortComplexity ===========================================
*/
void propPortComplexity(SimStruct *S)
{
CSignal_T cY = ssGetOutputPortComplexSignal( S, 0);
CSignal_T cU = ssGetInputPortComplexSignal( S, 0);
/* if input is complex, then output must be complex
*/
if ( cU == COMPLEX_YES )
{
/* if output complexity is not known then set it
*/
if ( cY == COMPLEX_INHERITED )
{
ssSetOutputPortComplexSignal(S, 0, COMPLEX_YES);
}
/* if the output is real, then an error has occurred
*/
else if ( cY == COMPLEX_NO )
{
ssSetErrorStatus(S,"Output is REAL, but input is COMPLEX.");
return;
}
}
/* if input is real then output must be real
*/
else if( cU == COMPLEX_NO )
{
/* if output complexity is not known then set it
*/
if ( cY == COMPLEX_INHERITED )
{
ssSetOutputPortComplexSignal(S, 0, COMPLEX_NO);
}
/* if the output is complex, then an error has occurred
*/
else if ( cY == COMPLEX_YES )
{
ssSetErrorStatus(S,"Output is COMPLEX, but input is REAL.");
return;
}
}
else /* Input is COMPLEX_INHERITED) */
{
if ( cY == COMPLEX_NO )
{
ssSetInputPortComplexSignal(S, 0, COMPLEX_NO );
}
else if ( cY == COMPLEX_YES )
{
ssSetInputPortComplexSignal(S, 0, COMPLEX_YES );
}
}
}
static void mdlSetOutputPortComplexSignal(SimStruct *S, int_T port,
int_T oPortComplexSignal)
{
/* Set the complex signal of the output ports */
ssSetOutputPortComplexSignal(S, 0, oPortComplexSignal);
if(oPortComplexSignal == COMPLEX_NO){
/* All inputs must be real */
int_T i;
for (i = 0; i < 2; i++) {
int_T iPortComplexSignal = ssGetInputPortComplexSignal(S, i);
if(iPortComplexSignal == COMPLEX_INHERITED){
ssSetInputPortComplexSignal(S, i, COMPLEX_NO);
} else if(iPortComplexSignal == COMPLEX_YES){
ssSetErrorStatus(S, "The output port is a 'real' signal. "
"All input ports must be 'real' signals.");
}
}
}else{
/*
* Output port is a complex signal. Report an error, if all
* inputs are real.
*/
int_T i;
boolean_T realInputs = true;
for (i = 0; i < 2; i++) {
if(ssGetInputPortComplexSignal(S, i) != COMPLEX_NO){
realInputs = false;
break;
}
}
if(realInputs){
ssSetErrorStatus(S, "Input port and output port complex signal "
"mismatch. All input ports are 'real' signal. "
"The output port must be a 'real' signal.");
}
}
}
/* Function: mdlOutputs =======================================================
* Abstract:
* In this function, you compute the outputs of your S-function
* block. Generally outputs are placed in the output vector(s),
* ssGetOutputPortSignal.
*/
static void mdlOutputs(SimStruct *S, int_T tid)
{
const void *pVoidIn = (const void *) ssGetInputPortSignal(S, 0);
void *pVoidOut = ssGetOutputPortSignal(S,0);
int regionIdx = 0;
boolean_T inIsComplex = (ssGetInputPortComplexSignal(S,0) == COMPLEX_YES);
int dataSize = ssGetDataTypeSize( S, ssGetInputPortDataType( S, 0 ) );
int dataWidth = ssGetInputPortWidth(S,0);
unsigned int idx = 0;
char * pCharInBase = NULL;
char * pCharOutBase = NULL;
char * pCharIn = NULL;
char * pCharOut =NULL;
uint32_T regionValue = 0;
fxpStorageContainerCategory inStorageContainerCategory;
fxpStorageContainerCategory outStorageContainerCategory;
DTypeId dTypeId;
if ( inIsComplex )
{
dataWidth = 2 * dataWidth;
}
dTypeId = ssGetInputPortDataType(S,0);
inStorageContainerCategory = ssGetDataTypeStorageContainCat(S,dTypeId);
dTypeId = ssGetOutputPortDataType(S,0);
outStorageContainerCategory = ssGetDataTypeStorageContainCat(S,dTypeId);
if(inStorageContainerCategory != outStorageContainerCategory)
{
ssSetErrorStatus(S, "Input and output have different container categories");
return;
}
if(inStorageContainerCategory == FXP_STORAGE_DOUBLE ||
inStorageContainerCategory == FXP_STORAGE_SINGLE ||
inStorageContainerCategory == FXP_STORAGE_SCALEDDOUBLE)
{
memcpy( pVoidOut, pVoidIn, dataWidth * dataSize );
}
else /*are fixed point*/
{
pCharInBase = (char *) pVoidIn;
pCharOutBase = (char *) pVoidOut;
for(idx = 0; idx < dataWidth; idx ++)
{
pCharIn = &pCharInBase[ idx * dataSize ];
pCharOut = &pCharOutBase[ idx * dataSize ];
for (regionIdx = 0; regionIdx < FXP_NUM_CHUNKS; regionIdx++)
{
regionValue = ssFxpGetU32BitRegion(S,
pCharIn,
dTypeId,
regionIdx);
ssFxpSetU32BitRegion(S,
pCharOut,
dTypeId,
regionValue,
regionIdx);
}
}
}
return;
} /* end mdlOutputs */
static void mdlOutputs(SimStruct *S, int_T tid)
{
/*
* detect which inputs are complex or not
*/
boolean_T u0IsComplex = ssGetInputPortComplexSignal(S, 0) == COMPLEX_YES;
boolean_T u1IsComplex = ssGetInputPortComplexSignal(S, 1) == COMPLEX_YES;
boolean_T yIsComplex = ssGetOutputPortComplexSignal(S, 0)== COMPLEX_YES;
DTypeId dType = ssGetOutputPortDataType(S,0);
InputPtrsType u0VPtr = ssGetInputPortSignalPtrs(S,0);
InputPtrsType u1VPtr = ssGetInputPortSignalPtrs(S,1);
int_T width = ssGetInputPortWidth(S,0);
int_T i;
switch (dType) {
case (SS_DOUBLE): {
real_T *y = (real_T *)ssGetOutputPortSignal(S,0);
real_T yr = 0.0; /* real part of the result */
real_T yi = 0.0; /* imag part of the result */
InputRealPtrsType u0Ptr = (InputRealPtrsType)u0VPtr;
InputRealPtrsType u1Ptr = (InputRealPtrsType)u1VPtr;
if(!yIsComplex){
/* both inputs are real */
for (i = 0; i < width; i++) {
yr += (**u0Ptr++) * (**u1Ptr++);
}
} else {
/* At least one if the inputs is complex. */
for (i = 0; i < width; i++) {
real_T u0r = u0Ptr[i][0];
real_T u0i = (u0IsComplex)? - u0Ptr[i][1] : 0.0;
real_T u1r = u1Ptr[i][0];
real_T u1i = (u1IsComplex)? u1Ptr[i][1] : 0.0;
yr += (u0r * u1r - u0i * u1i);
yi += (u0r * u1i + u0i * u1r);
}
}
/* Update output */
y[0] = yr;
if (yIsComplex) {
y[1] = yi;
}
}
break;
case (SS_SINGLE): {
real32_T *y = (real32_T *)ssGetOutputPortSignal(S,0);
real32_T yr = 0.0F; /* real part of the result */
real32_T yi = 0.0F; /* imag part of the result */
if(!yIsComplex){
/* both inputs are real */
for (i = 0; i < width; i++) {
const real32_T *u0Ptr = u0VPtr[i];
const real32_T *u1Ptr = u1VPtr[i];
yr += (*u0Ptr) * (*u1Ptr);
}
} else {
/* At least one if the inputs is complex. */
for (i = 0; i < width; i++) {
const real32_T *u0Ptr = u0VPtr[i];
const real32_T *u1Ptr = u1VPtr[i];
real32_T u0r = u0Ptr[0];
real32_T u0i = (u0IsComplex)? - u0Ptr[1] : 0.0F;
real32_T u1r = u1Ptr[0];
real32_T u1i = (u1IsComplex)? u1Ptr[1] : 0.0F;
yr += (u0r * u1r - u0i * u1i);
yi += (u0r * u1i + u0i * u1r);
}
}
/* Update output */
y[0] = yr;
if (yIsComplex) {
y[1] = yi;
}
}
break;
}
}
