/*
* AP cpu's call this to sync up protected mode.
*
* WARNING! We must ensure that the cpu is sufficiently initialized to
* be able to use to the FP for our optimized bzero/bcopy code before
* we enter more mainstream C code.
*
* WARNING! %fs is not set up on entry. This routine sets up %fs.
*/
void
init_secondary(void)
{
int gsel_tss;
int x, myid = bootAP;
u_int cr0;
struct mdglobaldata *md;
struct privatespace *ps;
ps = &CPU_prvspace[myid];
gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
gdt_segs[GPROC0_SEL].ssd_base =
(int) &ps->mdglobaldata.gd_common_tss;
ps->mdglobaldata.mi.gd_prvspace = ps;
for (x = 0; x < NGDT; x++) {
ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
}
r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
r_gdt.rd_base = (int) &gdt[myid * NGDT];
lgdt(&r_gdt); /* does magic intra-segment return */
lidt(&r_idt);
lldt(_default_ldt);
mdcpu->gd_currentldt = _default_ldt;
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
md->gd_common_tssd = *md->gd_tss_gdt;
ltr(gsel_tss);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
cr0 = rcr0();
cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
load_cr0(cr0);
pmap_set_opt(); /* PSE/4MB pages, etc */
/* set up CPU registers and state */
cpu_setregs();
/* set up FPU state on the AP */
npxinit(__INITIAL_NPXCW__);
/* set up SSE registers */
enable_sse();
}
/* setup APM GDT discriptors */
static void
setup_apm_gdt(u_int code32_base, u_int code16_base, u_int data_base, u_int code_limit, u_int data_limit)
{
/* setup 32bit code segment */
gdt_segs[GAPMCODE32_SEL].ssd_base = code32_base;
gdt_segs[GAPMCODE32_SEL].ssd_limit = code_limit;
/* setup 16bit code segment */
gdt_segs[GAPMCODE16_SEL].ssd_base = code16_base;
gdt_segs[GAPMCODE16_SEL].ssd_limit = code_limit;
/* setup data segment */
gdt_segs[GAPMDATA_SEL ].ssd_base = data_base;
gdt_segs[GAPMDATA_SEL ].ssd_limit = data_limit;
/* reflect these changes on physical GDT */
ssdtosd(gdt_segs + GAPMCODE32_SEL, &gdt[GAPMCODE32_SEL].sd);
ssdtosd(gdt_segs + GAPMCODE16_SEL, &gdt[GAPMCODE16_SEL].sd);
ssdtosd(gdt_segs + GAPMDATA_SEL , &gdt[GAPMDATA_SEL ].sd);
}
int
start_all_aps(void)
{
int x,apic_id, cpu;
struct pcpu *pc;
mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
/* set up temporary P==V mapping for AP boot */
/* XXX this is a hack, we should boot the AP on its own stack/PTD */
/* start each AP */
for (cpu = 1; cpu < mp_ncpus; cpu++) {
apic_id = cpu_apic_ids[cpu];
bootAP = cpu;
bootAPgdt = gdt + (512*cpu);
/* Get per-cpu data */
pc = &__pcpu[bootAP];
pcpu_init(pc, bootAP, sizeof(struct pcpu));
dpcpu_init((void *)kmem_alloc(kernel_map, DPCPU_SIZE), bootAP);
pc->pc_apic_id = cpu_apic_ids[bootAP];
pc->pc_prvspace = pc;
pc->pc_curthread = 0;
gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
PT_SET_MA(bootAPgdt, VTOM(bootAPgdt) | PG_V | PG_RW);
bzero(bootAPgdt, PAGE_SIZE);
for (x = 0; x < NGDT; x++)
ssdtosd(&gdt_segs[x], &bootAPgdt[x].sd);
PT_SET_MA(bootAPgdt, vtomach(bootAPgdt) | PG_V);
#ifdef notyet
if (HYPERVISOR_vcpu_op(VCPUOP_get_physid, cpu, &cpu_id) == 0) {
apicid = xen_vcpu_physid_to_x86_apicid(cpu_id.phys_id);
acpiid = xen_vcpu_physid_to_x86_acpiid(cpu_id.phys_id);
#ifdef CONFIG_ACPI
if (acpiid != 0xff)
x86_acpiid_to_apicid[acpiid] = apicid;
#endif
}
#endif
/* attempt to start the Application Processor */
if (!start_ap(cpu)) {
printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
/* better panic as the AP may be running loose */
printf("panic y/n? [y] ");
if (cngetc() != 'n')
panic("bye-bye");
}
CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
}
pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
/* number of APs actually started */
return mp_naps;
}
/*
* AP cpu's call this to sync up protected mode.
*
* WARNING! %gs is not set up on entry. This routine sets up %gs.
*/
void
init_secondary(void)
{
int gsel_tss;
int x, myid = bootAP;
u_int64_t msr, cr0;
struct mdglobaldata *md;
struct privatespace *ps;
ps = &CPU_prvspace[myid];
gdt_segs[GPROC0_SEL].ssd_base =
(long) &ps->mdglobaldata.gd_common_tss;
ps->mdglobaldata.mi.gd_prvspace = ps;
/* We fill the 32-bit segment descriptors */
for (x = 0; x < NGDT; x++) {
if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
}
/* And now a 64-bit one */
ssdtosyssd(&gdt_segs[GPROC0_SEL],
(struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
r_gdt.rd_base = (long) &gdt[myid * NGDT];
lgdt(&r_gdt); /* does magic intra-segment return */
/* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
wrmsr(MSR_FSBASE, 0); /* User value */
wrmsr(MSR_GSBASE, (u_int64_t)ps);
wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
#if 0
lldt(_default_ldt);
mdcpu->gd_currentldt = _default_ldt;
#endif
gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
#if 0 /* JG XXX */
md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
#endif
md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
md->gd_common_tssd = *md->gd_tss_gdt;
/* double fault stack */
md->gd_common_tss.tss_ist1 =
(long)&md->mi.gd_prvspace->idlestack[
sizeof(md->mi.gd_prvspace->idlestack)];
ltr(gsel_tss);
/*
* Set to a known state:
* Set by mpboot.s: CR0_PG, CR0_PE
* Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
*/
cr0 = rcr0();
cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
load_cr0(cr0);
/* Set up the fast syscall stuff */
msr = rdmsr(MSR_EFER) | EFER_SCE;
wrmsr(MSR_EFER, msr);
wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
wrmsr(MSR_STAR, msr);
wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
pmap_set_opt(); /* PSE/4MB pages, etc */
pmap_init_pat(); /* Page Attribute Table */
/* set up CPU registers and state */
cpu_setregs();
/* set up SSE/NX registers */
initializecpu(myid);
/* set up FPU state on the AP */
npxinit(__INITIAL_FPUCW__);
/* disable the APIC, just to be SURE */
lapic->svr &= ~APIC_SVR_ENABLE;
}
