void mctl_setup_dram_clock(__u32 clk) { __u32 i; __u32 reg_val; //setup DRAM PLL reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG); reg_val &= ~0x3; reg_val |= 0x1; //m factor reg_val &= ~(0x3<<4); reg_val |= 0x1<<4; //k factor reg_val &= ~(0x1f<<8); reg_val |= (standby_uldiv((__u64)clk, 24)&0x1f)<<8; //n factor reg_val &= ~(0x3<<16); reg_val |= 0x1<<16; //p factor reg_val &= ~(0x1<<29); //PLL on reg_val |= (__u32)0x1<<31; //PLL En mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val); standby_delay(0x100000); reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG); reg_val |= 0x1<<29; mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val); //reset GPS reg_val = mctl_read_w(DRAM_CCM_GPS_CLK_REG); reg_val &= ~0x3; mctl_write_w(DRAM_CCM_GPS_CLK_REG, reg_val); reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val |= (0x1<<26); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x20); reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val &= ~(0x1<<26); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); //open DRAMC AHB clock //close it first reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val &= ~(0x1<<14); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x1000); //then open it reg_val |= 0x1<<14; mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x1000); }
void mctl_setup_dram_clock(__u32 clk) { __u32 reg_val; #if defined(CONFIG_ARCH_SUN4I) const __u32 clocks = 0x1; #elif defined(CONFIG_ARCH_SUN5I) const __u32 clocks = 0x3; #else #error Unsupported sunxi architecture. #endif //setup DRAM PLL reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG); reg_val &= ~0x3; reg_val |= 0x1; //m factor reg_val &= ~(0x3<<4); reg_val |= 0x1<<4; //k factor reg_val &= ~(0x1f<<8); reg_val |= (standby_uldiv((__u64)clk, 24)&0x1f)<<8; //n factor reg_val &= ~(0x3<<16); reg_val |= 0x1<<16; //p factor reg_val &= ~(0x1<<29); //PLL on reg_val |= (__u32)0x1<<31; //PLL En mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val); standby_delay(0x100000); reg_val = mctl_read_w(DRAM_CCM_SDRAM_PLL_REG); reg_val |= 0x1<<29; mctl_write_w(DRAM_CCM_SDRAM_PLL_REG, reg_val); #if defined(CONFIG_ARCH_SUN4I) //reset GPS reg_val = mctl_read_w(DRAM_CCM_GPS_CLK_REG); reg_val &= ~0x3; mctl_write_w(DRAM_CCM_GPS_CLK_REG, reg_val); reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val |= (0x1<<26); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x20); reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val &= ~(0x1<<26); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); #elif defined(CONFIG_ARCH_SUN5I) //setup MBUS clock reg_val &= (0x1<<31)|(0x2<<24)|(0x1); mctl_write_w(DRAM_CCM_MUS_CLK_REG, reg_val); #else #error Unsupported sunxi architecture. #endif //open DRAMC AHB clock ( & DLL register clock on sun5i ) //close it first reg_val = mctl_read_w(DRAM_CCM_AHB_GATE_REG); reg_val &= ~(clocks<<14); mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x1000); //then open it reg_val |= clocks<<14; mctl_write_w(DRAM_CCM_AHB_GATE_REG, reg_val); standby_delay(0x1000); }