int cpuint_init(void)
{
int cpunum;
int irqline;
/* loop over all CPUs */
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
{
/* reset the IRQ lines */
for (irqline = 0; irqline < MAX_IRQ_LINES; irqline++)
{
irq_line_state[cpunum][irqline] = CLEAR_LINE;
interrupt_vector[cpunum][irqline] =
irq_line_vector[cpunum][irqline] = cpunum_default_irq_vector(cpunum);
}
/* reset the IRQ event queues */
irq_event_index[cpunum] = 0;
}
/* set up some stuff to save */
state_save_set_current_tag(0);
state_save_register_UINT8("cpu", 0, "irq enable", interrupt_enable, cpu_gettotalcpu());
state_save_register_INT32("cpu", 0, "irq vector", &interrupt_vector[0][0],cpu_gettotalcpu() * MAX_IRQ_LINES);
state_save_register_UINT8("cpu", 0, "irqline state", &irq_line_state[0][0], cpu_gettotalcpu() * MAX_IRQ_LINES);
state_save_register_INT32("cpu", 0, "irqline vector", &irq_line_vector[0][0], cpu_gettotalcpu() * MAX_IRQ_LINES);
return 0;
}
void EEPROM_init(struct EEPROM_interface *interface)
{
intf = interface;
if ((1 << intf->address_bits) * intf->data_bits / 8 > MEMORY_SIZE)
{
usrintf_showmessage("EEPROM larger than eeprom.c allows");
return;
}
memset(eeprom_data,0xff,(1 << intf->address_bits) * intf->data_bits / 8);
serial_count = 0;
latch = 0;
reset_line = ASSERT_LINE;
clock_line = ASSERT_LINE;
eeprom_read_address = 0;
sending = 0;
if (intf->cmd_unlock) locked = 1;
else locked = 0;
state_save_register_UINT8("eeprom", 0, "data", eeprom_data, MEMORY_SIZE);
state_save_register_UINT8("eeprom", 0, "serial buffer", serial_buffer, SERIAL_BUFFER_LENGTH);
state_save_register_int ("eeprom", 0, "clock line", &clock_line);
state_save_register_int ("eeprom", 0, "reset line", &reset_line);
state_save_register_int ("eeprom", 0, "locked", &locked);
state_save_register_int ("eeprom", 0, "serial count", &serial_count);
state_save_register_int ("eeprom", 0, "latch", &latch);
state_save_register_int ("eeprom", 0, "reset delay", &reset_delay);
state_save_register_int ("eeprom", 0, "clock count", &eeprom_clock_count);
state_save_register_int ("eeprom", 0, "data bits", &eeprom_data_bits);
state_save_register_int ("eeprom", 0, "address", &eeprom_read_address);
}
void volfied_cchip_init(void)
{
cchip_ram=auto_malloc(0x400 * 8);
state_save_register_UINT8("volfied", 0, "cc_bank", ¤t_bank, 1);
state_save_register_UINT8("volfied", 0, "cc_data", ¤t_cmd, 1);
state_save_register_UINT8("volfied", 0, "cc_flag", ¤t_flag, 1);
state_save_register_UINT8("volfied", 0, "cc_port", &cc_port, 1);
state_save_register_UINT8("volfied", 0, "cc_ram", cchip_ram, 0x400 * 8);
}
static DRIVER_INIT( opwolfb )
{
/* bootleg needs different range of raw gun coords */
opwolf_gun_xoffs = -2;
opwolf_gun_yoffs = 17;
/* (there are other sound vars that may need saving too) */
state_save_register_UINT8("sound2", 0, "registers", adpcm_b, 8);
state_save_register_UINT8("sound3", 0, "registers", adpcm_c, 8);
}
ROM_END
static DRIVER_INIT( opwolf )
{
opwolf_gun_xoffs = 0;
opwolf_gun_yoffs = 0;
/* (there are other sound vars that may need saving too) */
state_save_register_UINT8("sound2", 0, "registers", adpcm_b, 8);
state_save_register_UINT8("sound3", 0, "registers", adpcm_c, 8);
}
void arm_init(void)
{
int cpu = cpu_getactivecpu(),i;
char buf[8];
for (i=0; i<kNumRegisters; i++) {
sprintf(buf,"R%d",i);
state_save_register_UINT32("arm", cpu, buf, &arm.sArmRegister[i], 4);
}
state_save_register_UINT8("arm", cpu, "IRQ", &arm.pendingIrq, 1);
state_save_register_UINT8("arm", cpu, "FIQ", &arm.pendingFiq, 1);
return;
}
void volfied_cchip_init(void)
{
state_save_register_int ("volfied", 0, "cc_bank", ¤t_bank);
state_save_register_int ("volfied", 0, "cc_data", ¤t_data);
state_save_register_int ("volfied", 0, "cc_flag", ¤t_flag);
state_save_register_UINT8("volfied", 0, "cc_port", &cc_port, 1);
}
ROM_END
/*************************************
*
* Driver initialization
*
*************************************/
static DRIVER_INIT( jaguar )
{
state_save_register_UINT32("jaguar", 0, "ram", jaguar_shared_ram, 0x200000 / 4);
state_save_register_UINT32("jaguar", 0, "cart", cart_base, 0x600000 / 4);
state_save_register_UINT32("jaguar", 0, "gpu_clut", jaguar_gpu_clut, 0x000400 / 4);
state_save_register_UINT32("jaguar", 0, "gpu_ram", jaguar_gpu_ram, 0x001000 / 4);
state_save_register_UINT32("jaguar", 0, "dspram", jaguar_dsp_ram, 0x002000 / 4);
state_save_register_UINT32("jaguar", 0, "joystick_data", &joystick_data, 1);
state_save_register_UINT8("jaguar", 0, "eeprom_enable", &eeprom_enable, 1);
cojag_draw_crosshair = FALSE;
/* init the sound system and install DSP speedups */
cojag_sound_init();
}
static void at28c16_init( int chip )
{
struct at28c16_chip *c;
if( chip >= MAX_AT28C16_CHIPS )
{
logerror( "at28c16_init: invalid chip %d\n", chip );
return;
}
c = &at28c16[ chip ];
c->a9_12v = 0;
memset( c->data, 0, DATA_SIZE );
memset( c->id, 0, ID_SIZE );
state_save_register_UINT8( "at28c16", chip, "data", c->data, DATA_SIZE );
state_save_register_UINT8( "at28c16", chip, "id", c->id, ID_SIZE );
state_save_register_UINT8( "at28c16", chip, "a9_12v", &c->a9_12v, 1 );
}
void am53cf96_init( struct AM53CF96interface *interface )
{
const struct hard_disk_info *hdinfo;
// save interface pointer for later
intf = interface;
memset(scsi_regs, 0, sizeof(scsi_regs));
// try to open the disk
if (interface->device == AM53CF96_DEVICE_HDD)
{
disk = hard_disk_open(get_disk_handle(0));
if (!disk)
{
logerror("53cf96: no disk found!\n");
}
else
{
hdinfo = hard_disk_get_info(disk);
if (hdinfo->sectorbytes != 512)
{
logerror("53cf96: Error! invalid sector size %d\n", hdinfo->sectorbytes);
}
}
}
else if (interface->device == AM53CF96_DEVICE_CDROM)
{
logerror("53cf96: CDROM not yet supported!\n");
}
else
{
logerror("53cf96: unknown device type!\n");
}
state_save_register_UINT8("53cf96", 0, "registers", scsi_regs, 32);
state_save_register_UINT8("53cf96", 0, "fifo", fifo, 16);
state_save_register_UINT8("53cf96", 0, "fifo pointer", &fptr, 1);
state_save_register_UINT8("53cf96", 0, "last scsi-2 command", &last_cmd, 1);
state_save_register_UINT8("53cf96", 0, "transfer state", &xfer_state, 1);
state_save_register_int("53cf96", 0, "current lba", &lba);
state_save_register_int("53cf96", 0, "blocks to read", &blocks);
}
static void m6502_state_register(const char *type)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT16(type, cpu, "PC", &m6502.pc.w.l, 2);
state_save_register_UINT16(type, cpu, "SP", &m6502.sp.w.l, 2);
state_save_register_UINT8 (type, cpu, "P", &m6502.p, 1);
state_save_register_UINT8 (type, cpu, "A", &m6502.a, 1);
state_save_register_UINT8 (type, cpu, "X", &m6502.x, 1);
state_save_register_UINT8 (type, cpu, "Y", &m6502.y, 1);
state_save_register_UINT8 (type, cpu, "pending", &m6502.pending_irq, 1);
state_save_register_UINT8 (type, cpu, "after_cli", &m6502.after_cli, 1);
state_save_register_UINT8 (type, cpu, "nmi_state", &m6502.nmi_state, 1);
state_save_register_UINT8 (type, cpu, "irq_state", &m6502.irq_state, 1);
state_save_register_UINT8 (type, cpu, "so_state", &m6502.so_state, 1);
}
ROM_END
static void init_xmen(void)
{
konami_rom_deinterleave_2(REGION_GFX1);
konami_rom_deinterleave_4(REGION_GFX2);
state_save_register_UINT8("main", 0, "sound bank", &sound_curbank, 1);
state_save_register_func_postload(sound_reset_bank);
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
/*#if (HAS_HD63705) */
/* if(SUBTYPE!=SUBTYPE_HD63705) */
/*#endif */
/* PC |= ~AMASK; */
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} /* CC & IFLAG */
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void state_register(const char *type)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT8(type, cpu, "A", &A, 1);
state_save_register_UINT16(type, cpu, "PC", &PC, 1);
state_save_register_UINT16(type, cpu, "S", &S, 1);
state_save_register_UINT8(type, cpu, "X", &X, 1);
state_save_register_UINT8(type, cpu, "CC", &CC, 1);
state_save_register_UINT16(type, cpu, "PENDING", &m6805.pending_interrupts, 1);
state_save_register_INT32(type, cpu, "IRQ_STATE", &m6805.irq_state[0], 1);
}
static void m6805_init(void)
{
state_register("m6805");
}
int TMS9928A_start(int which, int model, unsigned int vram) {
/* 4 or 16 kB vram please */
if (! ((vram == 0x1000) || (vram == 0x4000) || (vram == 0x2000)) )
return 1;
tms[which].model = model;
/* Video RAM */
tms[which].vramsize = vram;
tms[which].vMem = (UINT8*) malloc (vram);
if (!tms[which].vMem) return (1);
memset (tms[which].vMem, 0, vram);
/* Sprite back buffer */
tms[which].dBackMem = (UINT8*)malloc (IMAGE_SIZE);
if (!tms[which].dBackMem) {
free (tms[which].vMem);
return 1;
}
/* dirty buffers */
tms[which].DirtyName = (char*)malloc (MAX_DIRTY_NAME);
if (!tms[which].DirtyName) {
free (tms[which].vMem);
free (tms[which].dBackMem);
return 1;
}
tms[which].DirtyPattern = (char*)malloc (MAX_DIRTY_PATTERN);
if (!tms[which].DirtyPattern) {
free (tms[which].vMem);
free (tms[which].DirtyName);
free (tms[which].dBackMem);
return 1;
}
tms[which].DirtyColour = (char*)malloc (MAX_DIRTY_COLOUR);
if (!tms[which].DirtyColour) {
free (tms[which].vMem);
free (tms[which].DirtyName);
free (tms[which].DirtyPattern);
free (tms[which].dBackMem);
return 1;
}
/* back bitmap */
tms[which].tmpbmp = bitmap_alloc (256, 192);
if (!tms[which].tmpbmp) {
free (tms[which].vMem);
free (tms[which].dBackMem);
free (tms[which].DirtyName);
free (tms[which].DirtyPattern);
free (tms[which].DirtyColour);
return 1;
}
/* sprite bitmap */
tms[which].tmpsbmp = bitmap_alloc (256, 192);
if (!tms[which].tmpsbmp) {
free (tms[which].vMem);
free (tms[which].dBackMem);
free (tms[which].DirtyName);
free (tms[which].DirtyPattern);
free (tms[which].DirtyColour);
return 1;
}
TMS9928A_reset (which);
tms[which].LimitSprites = 1;
state_save_register_UINT8 ("tms9928a", which, "R0", &tms[which].Regs[0], 1);
state_save_register_UINT8 ("tms9928a", which, "R1", &tms[which].Regs[1], 1);
state_save_register_UINT8 ("tms9928a", which, "R2", &tms[which].Regs[2], 1);
state_save_register_UINT8 ("tms9928a", which, "R3", &tms[which].Regs[3], 1);
state_save_register_UINT8 ("tms9928a", which, "R4", &tms[which].Regs[4], 1);
state_save_register_UINT8 ("tms9928a", which, "R5", &tms[which].Regs[5], 1);
state_save_register_UINT8 ("tms9928a", which, "R6", &tms[which].Regs[6], 1);
state_save_register_UINT8 ("tms9928a", which, "R7", &tms[which].Regs[7], 1);
state_save_register_UINT8 ("tms9928a", which, "S", &tms[which].StatusReg, 1);
state_save_register_UINT8 ("tms9928a", which, "read_ahead", &tms[which].ReadAhead, 1);
state_save_register_UINT8 ("tms9928a", which, "first_byte", &tms[which].FirstByte, 1);
state_save_register_UINT8 ("tms9928a", which, "latch", &tms[which].latch, 1);
state_save_register_UINT16 ("tms9928a", which, "vram_latch", (UINT16*)&tms[which].Addr, 1);
state_save_register_UINT8 ("tms9928a", which, "interrupt_line", &tms[which].INT, 1);
state_save_register_UINT8 ("tms9928a", which, "VRAM", tms[which].vMem, vram);
return 0;
}
void pia_init(int count)
{
int i;
for (i = 0; i < count; i++)
{
state_save_register_UINT8("6821pia", i, "in_a", &pia[i].in_a, 1);
state_save_register_UINT8("6821pia", i, "in_ca1", &pia[i].in_ca1, 1);
state_save_register_UINT8("6821pia", i, "in_ca2", &pia[i].in_ca2, 1);
state_save_register_UINT8("6821pia", i, "out_a", &pia[i].out_a, 1);
state_save_register_UINT8("6821pia", i, "out_ca2", &pia[i].out_ca2, 1);
state_save_register_UINT8("6821pia", i, "ddr_a", &pia[i].ddr_a, 1);
state_save_register_UINT8("6821pia", i, "ctl_a", &pia[i].ctl_a, 1);
state_save_register_UINT8("6821pia", i, "irq_a1", &pia[i].irq_a1, 1);
state_save_register_UINT8("6821pia", i, "irq_a2", &pia[i].irq_a2, 1);
state_save_register_UINT8("6821pia", i, "in_b", &pia[i].in_b, 1);
state_save_register_UINT8("6821pia", i, "in_cb1", &pia[i].in_cb1, 1);
state_save_register_UINT8("6821pia", i, "in_cb2", &pia[i].in_cb2, 1);
state_save_register_UINT8("6821pia", i, "out_b", &pia[i].out_b, 1);
state_save_register_UINT8("6821pia", i, "out_cb2", &pia[i].out_cb2, 1);
state_save_register_UINT8("6821pia", i, "ddr_b", &pia[i].ddr_b, 1);
state_save_register_UINT8("6821pia", i, "ctl_b", &pia[i].ctl_b, 1);
state_save_register_UINT8("6821pia", i, "irq_b1", &pia[i].irq_b1, 1);
state_save_register_UINT8("6821pia", i, "irq_b2", &pia[i].irq_b2, 1);
state_save_register_UINT8("6821pia", i, "in_set", &pia[i].in_set, 1);
state_save_register_func_postload(pia_postload_funcs[i]);
}
}
int ide_controller_init_custom(int which, struct ide_interface *intf, struct chd_file *diskhandle)
{
struct ide_state *ide = &idestate[which];
const struct hard_disk_info *hdinfo;
/* NULL interface is immediate failure */
if (!intf)
return 1;
/* reset the IDE state */
memset(ide, 0, sizeof(*ide));
ide->intf = intf;
/* set MAME harddisk handle */
ide->disk = hard_disk_open(diskhandle);
/* get and copy the geometry */
if (ide->disk)
{
hdinfo = hard_disk_get_info(ide->disk);
ide->num_cylinders = hdinfo->cylinders;
ide->num_sectors = hdinfo->sectors;
ide->num_heads = hdinfo->heads;
if (hdinfo->sectorbytes != IDE_DISK_SECTOR_SIZE)
/* wrong sector len */
return 1;
#if PRINTF_IDE_COMMANDS
printf("CHS: %d %d %d\n", ide->num_cylinders, ide->num_heads, ide->num_sectors);
#endif
}
/* build the features page */
ide_build_features(ide);
/* create a timer for timing status */
ide->last_status_timer = timer_alloc(NULL);
ide->reset_timer = timer_alloc(reset_callback);
/* register ide status */
state_save_register_UINT8 ("ide", which, "adapter_control", &ide->adapter_control, 1);
state_save_register_UINT8 ("ide", which, "status", &ide->status, 1);
state_save_register_UINT8 ("ide", which, "error", &ide->error, 1);
state_save_register_UINT8 ("ide", which, "command", &ide->command, 1);
state_save_register_UINT8 ("ide", which, "interrupt_pending", &ide->interrupt_pending, 1);
state_save_register_UINT8 ("ide", which, "precomp_offset", &ide->precomp_offset, 1);
state_save_register_UINT8 ("ide", which, "buffer", ide->buffer, IDE_DISK_SECTOR_SIZE);
state_save_register_UINT8 ("ide", which, "features", ide->features, IDE_DISK_SECTOR_SIZE);
state_save_register_UINT16("ide", which, "buffer_offset", &ide->buffer_offset, 1);
state_save_register_UINT16("ide", which, "sector_count", &ide->sector_count, 1);
state_save_register_UINT16("ide", which, "block_count", &ide->block_count, 1);
state_save_register_UINT16("ide", which, "sectors_until_int", &ide->sectors_until_int, 1);
state_save_register_UINT8 ("ide", which, "dma_active", &ide->dma_active, 1);
state_save_register_UINT8 ("ide", which, "dma_cpu", &ide->dma_cpu, 1);
state_save_register_UINT8 ("ide", which, "dma_address_xor", &ide->dma_address_xor, 1);
state_save_register_UINT8 ("ide", which, "dma_last_buffer", &ide->dma_last_buffer, 1);
state_save_register_UINT32("ide", which, "dma_address", &ide->dma_address, 1);
state_save_register_UINT32("ide", which, "dma_descriptor", &ide->dma_descriptor, 1);
state_save_register_UINT32("ide", which, "dma_bytes_left", &ide->dma_bytes_left, 1);
state_save_register_UINT8 ("ide", which, "bus_master_command", &ide->bus_master_command, 1);
state_save_register_UINT8 ("ide", which, "bus_master_status", &ide->bus_master_status, 1);
state_save_register_UINT32("ide", which, "bus_master_descriptor", &ide->bus_master_descriptor, 1);
state_save_register_UINT16("ide", which, "cur_cylinder", &ide->cur_cylinder, 1);
state_save_register_UINT8 ("ide", which, "cur_sector", &ide->cur_sector, 1);
state_save_register_UINT8 ("ide", which, "cur_head", &ide->cur_head, 1);
state_save_register_UINT8 ("ide", which, "cur_head_reg", &ide->cur_head_reg, 1);
state_save_register_UINT32("ide", which, "cur_lba", &ide->cur_lba, 1);
state_save_register_UINT16("ide", which, "num_cylinders", &ide->num_cylinders, 1);
state_save_register_UINT8 ("ide", which, "num_sectors", &ide->num_sectors, 1);
state_save_register_UINT8 ("ide", which, "num_heads", &ide->num_heads, 1);
state_save_register_UINT8 ("ide", which, "config_unknown", &ide->config_unknown, 1);
state_save_register_UINT8 ("ide", which, "config_register", ide->config_register, IDE_CONFIG_REGISTERS);
state_save_register_UINT8 ("ide", which, "config_register_num", &ide->config_register_num, 1);
state_save_register_int ("ide", which, "master_password_enable", &ide->master_password_enable);
state_save_register_int ("ide", which, "user_password_enable", &ide->user_password_enable);
return 0;
}
void pic16C5x_init(void)
{
int cpu = cpu_getactivecpu();
state_save_register_INT8("pic16C5x", cpu, "Old_Data", &old_data, 1);
state_save_register_UINT8("pic16C5x", cpu, "W", &R.W, 1);
state_save_register_UINT8("pic16C5x", cpu, "ALU", &R.ALU, 1);
state_save_register_UINT8("pic16C5x", cpu, "Option", &R.OPTION, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack0", &R.STACK[0], 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack1", &R.STACK[1], 1);
state_save_register_UINT16("pic16C5x", cpu, "PC", &R.PC, 1);
state_save_register_UINT16("pic16C5x", cpu, "PrevPC", &R.PREVPC, 1);
state_save_register_UINT16("pic16C5x", cpu, "Config", &R.CONFIG, 1);
state_save_register_UINT32("pic16C5x", cpu, "Opcode", &R.opcode.d, 1);
state_save_register_INT32("pic16C5x", cpu, "Delay_Timer", &delay_timer, 1);
state_save_register_INT32("pic16C5x", cpu, "PIC_model", &picmodel, 1);
state_save_register_INT32("pic16C5x", cpu, "Reset_Vector", &pic16C5x_reset_vector, 1);
}
static void AY8910_statesave(int chip)
{
struct AY8910 *PSG = &AYPSG[chip];
state_save_register_INT32("AY8910", chip, "register_latch", &PSG->register_latch, 1);
state_save_register_UINT8("AY8910", chip, "Regs", PSG->Regs, 8);
state_save_register_INT32("AY8910", chip, "lastEnable", &PSG->lastEnable, 1);
state_save_register_INT32("AY8910", chip, "PeriodA", &PSG->PeriodA, 1);
state_save_register_INT32("AY8910", chip, "PeriodB", &PSG->PeriodB, 1);
state_save_register_INT32("AY8910", chip, "PeriodC", &PSG->PeriodC, 1);
state_save_register_INT32("AY8910", chip, "PeriodN", &PSG->PeriodN, 1);
state_save_register_INT32("AY8910", chip, "PeriodE", &PSG->PeriodE, 1);
state_save_register_INT32("AY8910", chip, "CountA", &PSG->CountA, 1);
state_save_register_INT32("AY8910", chip, "CountB", &PSG->CountB, 1);
state_save_register_INT32("AY8910", chip, "CountC", &PSG->CountC, 1);
state_save_register_INT32("AY8910", chip, "CountN", &PSG->CountN, 1);
state_save_register_INT32("AY8910", chip, "CountE", &PSG->CountE, 1);
state_save_register_UINT32("AY8910", chip, "VolA", &PSG->VolA, 1);
state_save_register_UINT32("AY8910", chip, "VolB", &PSG->VolB, 1);
state_save_register_UINT32("AY8910", chip, "VolC", &PSG->VolC, 1);
state_save_register_UINT32("AY8910", chip, "VolE", &PSG->VolE, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeA", &PSG->EnvelopeA, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeB", &PSG->EnvelopeB, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeC", &PSG->EnvelopeC, 1);
state_save_register_UINT8("AY8910", chip, "OutputA", &PSG->OutputA, 1);
state_save_register_UINT8("AY8910", chip, "OutputB", &PSG->OutputB, 1);
state_save_register_UINT8("AY8910", chip, "OutputC", &PSG->OutputC, 1);
state_save_register_UINT8("AY8910", chip, "OutputN", &PSG->OutputN, 1);
state_save_register_INT8("AY8910", chip, "CountEnv", &PSG->CountEnv, 1);
state_save_register_UINT8("AY8910", chip, "Hold", &PSG->Hold, 1);
state_save_register_UINT8("AY8910", chip, "Alternate", &PSG->Alternate, 1);
state_save_register_UINT8("AY8910", chip, "Attack", &PSG->Attack, 1);
state_save_register_UINT8("AY8910", chip, "Holding", &PSG->Holding, 1);
state_save_register_INT32("AY8910", chip, "RNG", &PSG->RNG, 1);
}
static void register_savestate(void)
{
state_save_register_UINT8("video", 0, "control_1", actfancr_control_1, 0x20);
state_save_register_UINT8("video", 0, "control_2", actfancr_control_2, 0x20);
}
static int TMS9928A_start (const TMS9928a_interface *intf) {
/* 4, 8 or 16 kB vram please */
if (! ((intf->vram == 0x1000) || (intf->vram == 0x2000) || (intf->vram == 0x4000)) )
return 1;
tms.model = intf->model;
tms.top_border = TMS_50HZ ? TOP_BORDER_50HZ : TOP_BORDER_60HZ;
tms.bottom_border = TMS_50HZ ? BOTTOM_BORDER_50HZ : BOTTOM_BORDER_60HZ;
tms.INTCallback = intf->int_callback;
/* Video RAM */
tms.vramsize = intf->vram;
tms.vMem = (UINT8*) auto_malloc (intf->vram);
if (!tms.vMem)
return 1;
memset (tms.vMem, 0, intf->vram);
/* Sprite back buffer */
tms.dBackMem = (UINT8*)auto_malloc (IMAGE_SIZE);
if (!tms.dBackMem)
return 1;
/* dirty buffers */
tms.DirtyName = (char*)auto_malloc (MAX_DIRTY_NAME);
if (!tms.DirtyName)
return 1;
tms.DirtyPattern = (char*)auto_malloc (MAX_DIRTY_PATTERN);
if (!tms.DirtyPattern)
return 1;
tms.DirtyColour = (char*)auto_malloc (MAX_DIRTY_COLOUR);
if (!tms.DirtyColour)
return 1;
/* back bitmap */
tms.tmpbmp = auto_bitmap_alloc (256, 192);
if (!tms.tmpbmp)
return 1;
TMS9928A_reset ();
tms.LimitSprites = 1;
state_save_register_UINT8 ("tms9928a", 0, "R0", &tms.Regs[0], 1);
state_save_register_UINT8 ("tms9928a", 0, "R1", &tms.Regs[1], 1);
state_save_register_UINT8 ("tms9928a", 0, "R2", &tms.Regs[2], 1);
state_save_register_UINT8 ("tms9928a", 0, "R3", &tms.Regs[3], 1);
state_save_register_UINT8 ("tms9928a", 0, "R4", &tms.Regs[4], 1);
state_save_register_UINT8 ("tms9928a", 0, "R5", &tms.Regs[5], 1);
state_save_register_UINT8 ("tms9928a", 0, "R6", &tms.Regs[6], 1);
state_save_register_UINT8 ("tms9928a", 0, "R7", &tms.Regs[7], 1);
state_save_register_UINT8 ("tms9928a", 0, "S", &tms.StatusReg, 1);
state_save_register_UINT8 ("tms9928a", 0, "read_ahead", &tms.ReadAhead, 1);
state_save_register_UINT8 ("tms9928a", 0, "first_byte", &tms.FirstByte, 1);
state_save_register_UINT8 ("tms9928a", 0, "latch", &tms.latch, 1);
state_save_register_UINT16 ("tms9928a", 0, "vram_latch", (UINT16*)&tms.Addr, 1);
state_save_register_UINT8 ("tms9928a", 0, "interrupt_line", &tms.INT, 1);
state_save_register_UINT8 ("tms9928a", 0, "VRAM", tms.vMem, intf->vram);
return 0;
}
