static int __btn_task(void)
{
int st;
printf("%s(): thread %d started.\n", __func__, thinkos_thread_self());
stm32_gpio_clock_en(STM32_GPIOA);
stm32_gpio_mode(PUSH_BTN, INPUT, 0);
btn_st = stm32_gpio_stat(PUSH_BTN) ? 1 : 0;
for (;;) {
thinkos_sleep(50);
/* process push button */
st = stm32_gpio_stat(PUSH_BTN) ? 1 : 0;
if (btn_st != st) {
btn_st = st;
thinkos_mutex_lock(btn_mutex);
btn_event = st ? BTN_PRESSED : BTN_RELEASED;
thinkos_mutex_unlock(btn_mutex);
}
}
return 0;
}
static int conf_start(void)
{
/* The application processor (AP) begins by driving the iCE40
CRESET_B pin Low, resetting the iCE40 FPGA. Similarly, the AP holds
the iCE40's SPI_SS_B pin Low. The AP must hold the CRESET_B pin Low
for at least 200 ns. Ultimately, the AP either releases the CRESET_B
pin and allows it to float High via the 10 KOhm pull-up resistor to
VCCIO_2 or drives CRESET_B High. */
/* The iCE40 FPGA enters SPI peripheral mode when the CRESET_B pin
returns High while the SPI_SS_B pin is Low. */
stm32_gpio_clr(ICE40_SPI_SS);
/* reset */
stm32_gpio_clr(ICE40_CRESET);
udelay(1);
stm32_gpio_set(ICE40_CRESET);
if (stm32_gpio_stat(ICE40_CDONE)) {
stm32_gpio_set(ICE40_SPI_SS);
return -1;
}
/* After driving CRESET_B High or allowing it to float High the AP must
wait a minimum of 300 µs, allowing the iCE40 FPGA to clear its
internal configuration memory */
udelay(300);
return 0;
}
/*
* Configure an ICE40 FPGA device
*/
int lattice_ice40_configure(const uint8_t * buf, unsigned int max)
{
int ret;
int n;
int i;
lattice_ice40_io_init(50000);
DCC_LOG2(LOG_TRACE, "bin=0x%08x max=%d", buf, max);
while ((ret = conf_start()) < 0) {
DCC_LOG(LOG_ERROR, "conf_start() failed!");
return ret;
}
for (n = 0; n < max; ++n) {
if (stm32_gpio_stat(ICE40_CDONE))
break;
conf_wr(buf[n]);
}
if (n >= max) {
for (i = 0; i < 128; ++i) {
if (stm32_gpio_stat(ICE40_CDONE))
break;
conf_wr(0x00);
}
if (!stm32_gpio_stat(ICE40_CDONE)) {
stm32_gpio_set(ICE40_SPI_SS);
return -2;
}
}
DCC_LOG1(LOG_TRACE, "%d bytes", n);
/* After the CDONE output pin goes High, send at least 49 additional
dummy bits, effectively 49 additional SPI_SCK
clock cycles measured from rising-edge to rising-edge. */
for (i = 0; i < 7; ++i)
conf_wr(0x00);
stm32_gpio_set(ICE40_SPI_SS);
return n;
}
bool jtag3ctrl_irq_status(void)
{
return stm32_gpio_stat(STM32_GPIOD, 6) ? true : false;
}
