static void stm32_stdclockconfig(void)
{
uint32_t regval;
volatile int32_t timeout;
#ifdef STM32_BOARD_USEHSI
/* Enable Internal High-Speed Clock (HSI) */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSION; /* Enable HSI */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSIRDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#else /* if STM32_BOARD_USEHSE */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
*/
if (timeout > 0)
{
/* Select regulator voltage output Scale 1 mode to support system
* frequencies up to 168 MHz.
*/
regval = getreg32(STM32_RCC_APB1ENR);
regval |= RCC_APB1ENR_PWREN;
putreg32(regval, STM32_RCC_APB1ENR);
regval = getreg32(STM32_PWR_CR);
regval &= ~PWR_CR_VOS_MASK;
regval |= PWR_CR_VOS_SCALE_1;
putreg32(regval, STM32_PWR_CR);
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_RTCPRE_MASK;
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
putreg32(regval, STM32_RCC_CFGR);
#endif
/* Set the PLL dividers and multipliers to configure the main PLL */
#ifdef STM32_BOARD_USEHSI
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
#else /* if STM32_BOARD_USEHSE */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
#endif
putreg32(regval, STM32_RCC_PLLCFG);
/* Enable the main PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
{
}
#if defined(CONFIG_STM32_STM32F429)
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
regval = getreg32(STM32_PWR_CR);
regval |= PWR_CR_ODEN;
putreg32(regval, STM32_PWR_CR);
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
{
}
regval = getreg32(STM32_PWR_CR);
regval |= PWR_CR_ODSWEN;
putreg32(regval, STM32_PWR_CR);
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
{
}
#endif
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef CONFIG_STM32_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
#else
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif
putreg32(regval, STM32_FLASH_ACR);
/* Select the main PLL as system clock source */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
{
}
#ifdef CONFIG_STM32_LTDC
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIR
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
putreg32(regval, STM32_RCC_PLLSAICFGR);
regval = getreg32(STM32_RCC_DCKCFGR);
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
putreg32(regval, STM32_RCC_DCKCFGR);
/* Enable PLLSAI */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLSAION;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLSAI is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
{
}
#endif
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO1 pin selects LSE as source.
*/
stm32_rcc_enablelse();
#endif
}
}
static void stm32_stdclockconfig(void)
{
uint32_t regval;
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
uint16_t pwrcr;
#endif
uint32_t pwr_vos;
bool flash_1ws;
/* Enable PWR clock from APB1 to give access to PWR_CR register */
regval = getreg32(STM32_RCC_APB1ENR);
regval |= RCC_APB1ENR_PWREN;
putreg32(regval, STM32_RCC_APB1ENR);
/* Go to the high performance voltage range 1 if necessary. In this mode,
* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported.
*
* Range 1: PLLVCO up to 96MHz in range 1 (1.8V)
* Range 2: PLLVCO up to 48MHz in range 2 (1.5V) (default)
* Range 3: PLLVCO up to 24MHz in range 3 (1.2V)
*
* Range 1: SYSCLK up to 32Mhz
* Range 2: SYSCLK up to 16Mhz
* Range 3: SYSCLK up to 4.2Mhz
*
* Range 1: Flash 1WS if SYSCLK > 16Mhz
* Range 2: Flash 1WS if SYSCLK > 8Mhz
* Range 3: Flash 1WS if SYSCLK > 2.1Mhz
*/
pwr_vos = PWR_CR_VOS_SCALE_2;
flash_1ws = false;
#ifdef STM32_PLL_FREQUENCY
if (STM32_PLL_FREQUENCY > 48000000)
{
pwr_vos = PWR_CR_VOS_SCALE_1;
}
#endif
if (STM32_SYSCLK_FREQUENCY > 16000000)
{
pwr_vos = PWR_CR_VOS_SCALE_1;
}
if ((pwr_vos == PWR_CR_VOS_SCALE_1 && STM32_SYSCLK_FREQUENCY > 16000000) ||
(pwr_vos == PWR_CR_VOS_SCALE_2 && STM32_SYSCLK_FREQUENCY > 8000000))
{
flash_1ws = true;
}
stm32_pwr_setvos(pwr_vos);
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
/* If RTC / LCD selects HSE as clock source, the RTC prescaler
* needs to be set before HSEON bit is set.
*/
/* The RTC domain has write access denied after reset,
* you have to enable write access using DBP bit in the PWR CR
* register before to selecting the clock source ( and the PWR
* peripheral must be enabled)
*/
regval = getreg32(STM32_RCC_APB1ENR);
regval |= RCC_APB1ENR_PWREN;
putreg32(regval, STM32_RCC_APB1ENR);
pwrcr = getreg16(STM32_PWR_CR);
putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR);
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CSR);
regval &= ~RCC_CSR_RTCSEL_MASK;
regval |= RCC_CSR_RTCSEL_HSE;
putreg32(regval, STM32_RCC_CSR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_RTCPRE_MASK;
regval |= HSE_DIVISOR;
putreg32(regval, STM32_RCC_CR);
/* Restore the previous state of the DBP bit */
putreg32(regval, STM32_PWR_CR);
#endif
/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC))
/* The PLL is using the HSE, or the HSE is the system clock. In either
* case, we need to enable HSE clocking.
*/
if (!stm32_rcc_enablehse())
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or
* misconfiguration (for example, if no crystal is fitted on the board.
*/
return;
}
#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
/* The PLL is using the HSI, or the HSI is the system clock. In either
* case, we need to enable HSI clocking.
*/
regval = getreg32(STM32_RCC_CR); /* Enable the HSI */
regval |= RCC_CR_HSION;
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI clock is ready. Since this is an internal clock, no
* timeout is expected
*/
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0);
#endif
#if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI)
/* Increasing the CPU frequency (in the same voltage range):
*
* After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
* FLASH_ACR register. 32-bit access is enabled and prefetch is disabled.
* ST strongly recommends to use the following software sequences to tune the
* number of wait states needed to access the Flash memory with the CPU
* frequency.
*
* - Program the 64-bit access by setting the ACC64 bit in Flash access
* control register (FLASH_ACR)
* - Check that 64-bit access is taken into account by reading FLASH_ACR
* - Program 1 WS to the LATENCY bit in FLASH_ACR
* - Check that the new number of WS is taken into account by reading FLASH_ACR
* - Modify the CPU clock source by writing to the SW bits in the Clock
* configuration register (RCC_CFGR)
* - If needed, modify the CPU clock prescaler by writing to the HPRE bits in
* RCC_CFGR
* - Check that the new CPU clock source or/and the new CPU clock prescaler
* value is/are taken into account by reading the clock source status (SWS
* bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
* RCC_CFGR register
*/
regval = getreg32(STM32_FLASH_ACR);
regval |= FLASH_ACR_ACC64; /* 64-bit access mode */
putreg32(regval, STM32_FLASH_ACR);
if (flash_1ws)
{
regval |= FLASH_ACR_LATENCY; /* One wait state */
}
else
{
regval &= ~FLASH_ACR_LATENCY; /* Zero wait state */
}
putreg32(regval, STM32_FLASH_ACR);
/* Enable FLASH prefetch */
regval |= FLASH_ACR_PRFTEN;
putreg32(regval, STM32_FLASH_ACR);
#endif /* STM32_SYSCLK_SW != RCC_CFGR_SW_MSI */
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* If we are using the PLL, configure and start it */
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* Set the PLL divider and multiplier. NOTE: The PLL needs to be disabled
* to do these operation. We know this is the case here because pll_reset()
* was previously called by stm32_clockconfig().
*/
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK | RCC_CFGR_PLLDIV_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLMUL | STM32_CFGR_PLLDIV);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || \
defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if TIM9-10 Channel 1 selects LSE as input.
*
* TODO: There is another case where the LSE needs to
* be enabled: if TIM10-11 selects LSE as ETR Input.
*
*/
stm32_rcc_enablelse();
#endif
}
static void stm32_stdclockconfig(void)
{
uint32_t regval;
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or misconfiguration.
*/
return;
}
}
/* If this is a value-line part and we are using the HSE as the PLL */
# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
# endif
#endif
/* Value-line devices don't implement flash prefetch/waitstates */
#ifndef CONFIG_STM32_VALUELINE
/* Enable FLASH prefetch buffer and 2 wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* If we are using the PLL, configure and start it */
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
}
static void stm32_stdclockconfig(void)
{
uint32_t regval;
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or
* misconfiguration.
*/
return;
}
}
#endif
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Set flash wait states according to sysclk:
*
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
regval = getreg32(STM32_FLASH_ACR);
regval &= ~(FLASH_ACR_LATENCY_MASK);
#if STM32_SYSCLK_FREQUENCY <= 24000000
regval |= FLASH_ACR_LATENCY_0;
#elif STM32_SYSCLK_FREQUENCY <= 48000000
regval |= FLASH_ACR_LATENCY_1;
#else
regval |= FLASH_ACR_LATENCY_2;
#endif
regval |= FLASH_ACR_PRTFBE;
putreg32(regval, STM32_FLASH_ACR);
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if USARTx selects LSE as source.
*/
stm32_rcc_enablelse();
#endif
#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL
regval = getreg32(STM32_RCC_CFGR3);
regval |= RCC_CFGR3_HRTIM1SW;
putreg32(regval, STM32_RCC_CFGR3);
#endif
}
