Example #1
0
static int qspi_setup_iomux(void)
{
	int rv = 0;
#ifdef CONFIG_STM32_QSPI
	int i;

	for (i = 0; i < ARRAY_SIZE(qspi_af9_iomux); i++) {
		rv = stm32f2_gpio_config(&qspi_af9_iomux[i],
					 STM32F2_GPIO_ROLE_QSPI_AF9);
		if (rv)
			break;
	}

	for (i = 0; i < ARRAY_SIZE(qspi_af10_iomux); i++) {
		rv = stm32f2_gpio_config(&qspi_af10_iomux[i],
					 STM32F2_GPIO_ROLE_QSPI_AF10);
		if (rv)
			break;
	}
#endif /* CONFIG_STM32_QSPI */
	return rv;
}
Example #2
0
/*
 * Initialize LCD pins
 */
static int ltdc_setup_iomux(void)
{
	int rv = 0;
	int i;

	/*
	 * Connect GPIOs to FMC controller
	 */
	for (i = 0; i < ARRAY_SIZE(ltdc_iomux); i++) {
		rv = stm32f2_gpio_config(&ltdc_iomux[i],
				STM32F2_GPIO_ROLE_LTDC);
		if (rv)
			break;
	}

	return rv;
}
Example #3
0
/*
 * Init FMC/FSMC GPIOs based
 */
static int fmc_fsmc_setup_gpio(void)
{
	int rv = 0;
	int i;

	/*
	 * Connect GPIOs to FMC controller
	 */
	for (i = 0; i < ARRAY_SIZE(ext_ram_fsmc_fmc_gpio); i++) {
		rv = stm32f2_gpio_config(&ext_ram_fsmc_fmc_gpio[i],
				STM32F2_GPIO_ROLE_FMC);
		if (rv)
			goto out;
	}

	fsmc_gpio_init_done = 1;
out:
	return rv;
}
Example #4
0
/*
 * Configure GPIOs
 */
static int pwr_setup_gpio(void)
{
	struct stm32f2_gpio_dsc pwr_en_gpio[] = {
		{ STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_10 },	/* PWR_EN  */
		{ STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0  },	/* LCD_DIM */
	};
	int i, rv;

	for (i = 0; i < ARRAY_SIZE(pwr_en_gpio); i++) {
		rv = stm32f2_gpio_config(&pwr_en_gpio[i],
					 STM32F2_GPIO_ROLE_GPOUT);
		if (rv)
			goto out;

		rv = stm32f2_gpout_set(&pwr_en_gpio[i], 1);
		if (rv)
			goto out;
	}
out:
	return rv;
}
Example #5
0
/*
 * Setup external RAM.
 */
int dram_init(void)
{
	int				rv = 0;

#if 0
	static struct stm32f2_gpio_dsc	ctrl_gpio = {STM32F2_GPIO_PORT_I,
						     STM32F2_GPIO_PIN_9};

	rv = fsmc_nor_psram_init(CONFIG_SYS_RAM_CS,
			CONFIG_SYS_FSMC_PSRAM_BCR,
			CONFIG_SYS_FSMC_PSRAM_BTR,
#ifdef CONFIG_SYS_FSMC_PSRAM_BWTR
			CONFIG_SYS_FSMC_PSRAM_BWTR
#else
			(u32)-1
#endif
		);
	if (rv != 0)
		goto out;

	rv = stm32f2_gpio_config(&ctrl_gpio, STM32F2_GPIO_ROLE_GPOUT);
	if (rv != 0)
		goto out;

# if defined(CONFIG_SYS_RAM_BURST)
	/*
	 * FIXME: all this hardcoded stuff.
	 */

	/* Step.2 */
	stm32f2_gpout_set(&ctrl_gpio, 1);

	/* Step.3 */
	*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0010223E) = 0;

	/* Step.4-5 */
	stm32f2_gpout_set(&ctrl_gpio, 0);

	/* Step.6 */
	fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
			0x0010FFFF, -1);

	/* Step.7 */
	rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x000000);

	/* Step.8 */
	fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00005059,
			0x10000702, 0x10000602);

	/* Step.9 */
	stm32f2_gpout_set(&ctrl_gpio, 1);

	/* Step.10 */
	*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0110223E) = 0;

	/* Step.11 */
	stm32f2_gpout_set(&ctrl_gpio, 0);

	/* Step.12 */
	fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
			0x0010FFFF, -1);

	/* Step.13 */
	rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x01000000);

# else
	/*
	 * Switch PSRAM in the Asyncronous Read/Write Mode
	 */
	stm32f2_gpout_set(&ctrl_gpio, 0);
# endif /* CONFIG_SYS_RAM_BURST */

#endif
	/*
	 * Fill in global info with description of SRAM configuration
	 */
	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;

	rv = 0;
out:
	return rv;
}
Example #6
0
/*******************************************************************************
* Function Name  : disp_open
* Description    : Initializes and configures the Display
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
int disp_open(uint32_t FBAddr)
{
	int i, rv = 0;

	//-------------------------------------------------------------------------
	// Initialize the SDRAM
	//-------------------------------------------------------------------------
	//fmc_dram_init();
	
	//-------------------------------------------------------------------------
	// Connect GPIOs to FMC controller
	//-------------------------------------------------------------------------
	for (i = 0; i < ARRAY_SIZE(ext_tft_gpio); i++)
	{
		rv = stm32f2_gpio_config(&ext_tft_gpio[i]);
		if (rv != 0)
			return -1;
	}//for
	CHIP_ENB();
	CHIP_DSB();
	
	//-------------------------------------------------------------------------
	// Configure the LCD_SPI interface
	//-------------------------------------------------------------------------

	// Enable SPI clock
	LCD_SpiClkEnable();

	// Reset SPI peripheral
	LCD_SpiPeripReset();

	// SPI Config
	LCD_SPI->cr1 = 0x030C;
	LCD_SPI->i2scfgr &= ~((uint16_t)0x0800);
	LCD_SPI->crcpr = 7;

	// SPI enable
	LCD_SPI->cr1 |= 0x0040;
	//-------------------------------------------------------------------------

	// LCD low level initializing
	lcd_init();

	// Enable the LTDC Clock
	STM32_RCC->apb2enr |= ((uint32_t)0x04000000);

	// Enable the DMA2D Clock
	STM32_RCC->ahb1enr |= ((uint32_t)0x00800000);

	// Configure PLLSAI prescalers for LCD
	// Enable Pixel Clock
	// PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz
	// PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAI_N = 192 Mhz
	// PLLLCDCLK = PLLSAI_VCO Output/PLLSAI_R = 192/4 = 48 Mhz
	// LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDivR = 48/8 = 6 Mhz
	STM32_RCC->pllsaicfgr = (192 << 6) | (7 << 24) | (4 << 28);

	STM32_RCC->dckcfgr &= ~0x00030000;
	STM32_RCC->dckcfgr |=  0x00020000;

	// Enable PLLSAI Clock
	*((volatile uint32_t *)CR_PLLSAION_BB) = 1;

	// Wait for PLLSAI activation
	while ((STM32_RCC->cr & 0x20000000) == 0);

	//-------------------------------------------------------------------------
	// LTDC Configuration
	//-------------------------------------------------------------------------
	STM32_LTDC->sscr &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
	STM32_LTDC->sscr |= (0x00090000 | 1);

	STM32_LTDC->bpcr &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
	STM32_LTDC->bpcr |= (0x001D0000 | 3);

	STM32_LTDC->awcr &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
	STM32_LTDC->awcr |= (0x010D0000 | 323);

	STM32_LTDC->twcr &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
	STM32_LTDC->twcr |= (0x01170000 | 327);

	STM32_LTDC->gcr &= ((uint32_t)0x0FFE888F);

	STM32_LTDC->bccr &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);

	//-------------------------------------------------------------------------
	// Layer configuration
	//-------------------------------------------------------------------------
	STM32_LTDC_LAYER1->whpcr &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
	STM32_LTDC_LAYER1->whpcr  = (0x010D0000 | 30);

	STM32_LTDC_LAYER1->wvpcr &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
	STM32_LTDC_LAYER1->wvpcr  = (0x01430000 | 4);

	STM32_LTDC_LAYER1->pfcr  &= ~(LTDC_LxPFCR_PF);
	STM32_LTDC_LAYER1->pfcr   = 2;

	STM32_LTDC_LAYER1->dccr  &=  ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
	STM32_LTDC_LAYER1->dccr   = 0x00000000;

	STM32_LTDC_LAYER1->cacr  &= ~(LTDC_LxCACR_CONSTA);
	STM32_LTDC_LAYER1->cacr   = 255;

	STM32_LTDC_LAYER1->bfcr  &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
	STM32_LTDC_LAYER1->bfcr   = (1024 | 5);

	STM32_LTDC_LAYER1->cfbar &= ~(LTDC_LxCFBAR_CFBADD);
	STM32_LTDC_LAYER1->cfbar  = FBAddr;

	STM32_LTDC_LAYER1->cfblr &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
	STM32_LTDC_LAYER1->cfblr  = (0x01E00000 | 483);

	STM32_LTDC_LAYER1->cfblnr &= ~(LTDC_LxCFBLNR_CFBLNBR);
	STM32_LTDC_LAYER1->cfblnr  = 320;
	
	STM32_LTDC->gcr |= ((uint32_t)LTDC_GCR_DTEN);
	STM32_LTDC_LAYER1->cr |= ((uint32_t)LTDC_LxCR_LEN);
	STM32_LTDC->srcr = (uint32_t)LTDC_SRCR_IMR;

	//-------------------------------------------------------------------------
	// Enable The LCD
	//-------------------------------------------------------------------------
	STM32_LTDC->gcr |= ((uint32_t)LTDC_GCR_LTDCEN);

	return 0;
}//disp_open