bool stm32f4_probe(target *t) { bool f2 = false; uint32_t idcode; idcode = target_mem_read32(t, DBGMCU_IDCODE); idcode &= 0xFFF; if (idcode == 0x411) { /* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the * distinction with F205. Revision is also wrong (0x2000 instead * of 0x1000). See F40x/F41x errata. */ uint32_t cpuid = target_mem_read32(t, ARM_CPUID); if ((cpuid & 0xFFF0) == 0xC240) idcode = 0x413; else f2 = true; } switch(idcode) { case 0x419: /* 427/437 */ /* Second bank for 2M parts. */ stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12); stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16); stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17); /* Fall through for stuff common to F40x/F41x */ case 0x411: /* F205 */ case 0x413: /* F405 */ case 0x421: /* F446 */ case 0x423: /* F401 B/C RM0368 Rev.3 */ case 0x431: /* F411 RM0383 Rev.4 */ case 0x433: /* F401 D/E RM0368 Rev.3 */ t->driver = f2 ? stm32f2_driver_str : stm32f4_driver_str; if (!f2) target_add_ram(t, 0x10000000, 0x10000); target_add_ram(t, 0x20000000, 0x30000); stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0); stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4); stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5); target_add_commands(t, stm32f4_cmd_list, f2 ? "STM32F2" : "STM32F4"); break; case 0x449: /* F7x6 RM0385 Rev.2 */ t->driver = stm32f7_driver_str; target_add_ram(t, 0x00000000, 0x4000); target_add_ram(t, 0x20000000, 0x50000); stm32f4_add_flash(t, 0x8000000, 0x20000, 0x8000, 0); stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4); stm32f4_add_flash(t, 0x8040000, 0xC0000, 0x40000, 5); target_add_commands(t, stm32f4_cmd_list, "STM32F7"); break; default: return false; } t->idcode = idcode; return true; }
bool stm32f4_probe(target *t) { uint32_t idcode; idcode = target_mem_read32(t, DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x419: /* 427/437 */ /* Second bank for 2M parts. */ stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12); stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16); stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17); /* Fall through for stuff common to F40x/F41x */ case 0x411: /* Documented to be 0x413! This is what I read... */ case 0x413: /* F407VGT6 */ case 0x423: /* F401 B/C RM0368 Rev.3 */ case 0x431: /* F411 RM0383 Rev.4 */ case 0x433: /* F401 D/E RM0368 Rev.3 */ t->driver = stm32f4_driver_str; target_add_ram(t, 0x10000000, 0x10000); target_add_ram(t, 0x20000000, 0x30000); stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0); stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4); stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5); target_add_commands(t, stm32f4_cmd_list, "STM32F4"); return true; } return false; }
bool stm32f4_probe(target *t) { bool f2 = false; uint32_t idcode; idcode = target_mem_read32(t, DBGMCU_IDCODE); idcode &= 0xFFF; if (idcode == ID_STM32F20X) { /* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the * distinction with F205. Revision is also wrong (0x2000 instead * of 0x1000). See F40x/F41x errata. */ uint32_t cpuid = target_mem_read32(t, ARM_CPUID); if ((cpuid & 0xFFF0) == 0xC240) idcode = ID_STM32F40X; else f2 = true; } switch(idcode) { case ID_STM32F42X: /* 427/437 */ case ID_STM32F46X: /* 469/479 */ /* Second bank for 2M parts. */ stm32f4_add_flash(t, 0x8100000, 0x10000, 0x4000, 12); stm32f4_add_flash(t, 0x8110000, 0x10000, 0x10000, 16); stm32f4_add_flash(t, 0x8120000, 0xE0000, 0x20000, 17); /* Fall through for stuff common to F40x/F41x */ case ID_STM32F20X: /* F205 */ case ID_STM32F40X: /* F405 */ if (!f2) target_add_ram(t, 0x10000000, 0x10000); /* Fall through for devices w/o CCMRAM */ case ID_STM32F446: /* F446 */ case ID_STM32F401C: /* F401 B/C RM0368 Rev.3 */ case ID_STM32F411: /* F411 RM0383 Rev.4 */ case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */ case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */ t->driver = f2 ? stm32f2_driver_str : stm32f4_driver_str; target_add_ram(t, 0x20000000, 0x40000); stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0); stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4); stm32f4_add_flash(t, 0x8020000, 0xE0000, 0x20000, 5); target_add_commands(t, stm32f4_cmd_list, f2 ? "STM32F2" : "STM32F4"); break; case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */ t->driver = stm32f4_driver_str; target_add_ram(t, 0x20000000, 0x50000); stm32f4_add_flash(t, 0x8000000, 0x10000, 0x4000, 0); stm32f4_add_flash(t, 0x8010000, 0x10000, 0x10000, 4); stm32f4_add_flash(t, 0x8020000, 0x160000, 0x20000, 5); target_add_commands(t, stm32f4_cmd_list, "STM32F413"); break; case ID_STM32F74X: /* F74x RM0385 Rev.4 */ t->driver = stm32f7_driver_str; target_add_ram(t, 0x00000000, 0x4000); target_add_ram(t, 0x20000000, 0x50000); /* AXIM Flash access */ stm32f4_add_flash(t, 0x8000000, 0x20000, 0x8000, 0); stm32f4_add_flash(t, 0x8020000, 0x20000, 0x20000, 4); stm32f4_add_flash(t, 0x8040000, 0xC0000, 0x40000, 5); /* Flash aliased as ITCM */ stm32f4_add_flash(t, 0x0200000, 0x20000, 0x8000, 0); stm32f4_add_flash(t, 0x0220000, 0x20000, 0x20000, 4); stm32f4_add_flash(t, 0x0240000, 0xC0000, 0x40000, 5); target_add_commands(t, stm32f4_cmd_list, "STM32F74x"); break; case ID_STM32F76X: /* F76x F77x RM0410 */ t->driver = stm32f7_driver_str; target_add_ram(t, 0x00000000, 0x4000); target_add_ram(t, 0x20000000, 0x80000); /* AXIM Flash access */ stm32f4_add_flash(t, 0x8000000, 0x020000, 0x8000, 0); stm32f4_add_flash(t, 0x8020000, 0x020000, 0x20000, 4); stm32f4_add_flash(t, 0x8040000, 0x1C0000, 0x40000, 5); /* Flash aliased as ITCM */ stm32f4_add_flash(t, 0x200000, 0x020000, 0x8000, 0); stm32f4_add_flash(t, 0x220000, 0x020000, 0x20000, 4); stm32f4_add_flash(t, 0x240000, 0x1C0000, 0x40000, 5); target_add_commands(t, stm32f4_cmd_list, "STM32F76x"); break; case ID_STM32F72X: /* F72x F73x RM0431 */ t->driver = stm32f7_driver_str; target_add_ram(t, 0x00000000, 0x2000); target_add_ram(t, 0x20000000, 0x40000); stm32f4_add_flash(t, 0x8000000, 0x010000, 0x4000, 0); stm32f4_add_flash(t, 0x8010000, 0x010000, 0x10000, 4); stm32f4_add_flash(t, 0x8020000, 0x060000, 0x20000, 3); target_add_commands(t, stm32f4_cmd_list, "STM32F72x"); break; default: return false; } t->idcode = idcode; return true; }