static int stmpe_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; u8 mask = BIT(offset % 8); return stmpe_set_bits(stmpe, reg, mask, 0); }
static int stmpe_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); u8 mask = 1 << (offset % 8); stmpe_gpio_set(chip, offset, val); return stmpe_set_bits(stmpe, reg, mask, mask); }
static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) { struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; u8 reg = stmpe->regs[which + (offset / 8)]; u8 mask = BIT(offset % 8); /* * Some variants have single register for gpio set/clear functionality. * For them we need to write 0 to clear and 1 to set. */ if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); else stmpe_reg_write(stmpe, reg, mask); }