int set_low_bus_freq(void)
{
if (busfreq_suspended)
return 0;
if (bus_freq_scaling_initialized) {
/* can not enter low bus freq, when cpu is in higher freq
* or only have one working point */
if ((clk_get_rate(cpu_clk) >
cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate)
|| (cpu_wp_nr == 1)) {
return 0;
}
mutex_lock(&bus_freq_mutex);
stop_dvfs_per();
stop_sdram_autogating();
if (cpu_is_mx50())
enter_lpapm_mode_mx50();
else if (cpu_is_mx51())
enter_lpapm_mode_mx51();
else
enter_lpapm_mode_mx53();
mutex_unlock(&bus_freq_mutex);
}
return 0;
}
static ssize_t dvfsper_enable_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
if (strstr(buf, "1") != NULL) {
if (dvfs_enable(dev) != 0)
printk(KERN_ERR "Failed to start DVFS\n");
} else if (strstr(buf, "0") != NULL)
stop_dvfs_per();
return size;
}
int set_low_bus_freq(void)
{
int ret = 0;
unsigned long flags;
unsigned long lp_lpm_clk;
if (busfreq_suspended)
return ret;
if (low_bus_freq_mode || (clk_get_rate(cpu_clk) != GP_LPAPM_FREQ)) {
return ret;
}
stop_dvfs_per();
spin_lock_irqsave(&bus_freq_lock, flags);
lp_lpm_clk = clk_get_rate(periph_apm_clk) / 8;
/* Set the parent of peripheral_apm_clk to be pll1 */
clk_set_parent(periph_apm_clk, pll1);
/* Set the LP clocks */
clk_set_parent(main_bus_clk, periph_apm_clk);
clk_set_rate(axi_a_clk, clk_round_rate(axi_a_clk, lp_lpm_clk));
clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, lp_lpm_clk));
clk_set_rate(axi_c_clk, clk_round_rate(axi_c_clk, lp_lpm_clk));
clk_set_rate(emi_core_clk, clk_round_rate(emi_core_clk, lp_lpm_clk));
clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, lp_lpm_clk));
/* Set the emi_intr_clk to be at 24MHz. */
clk_set_rate(emi_intr_clk, clk_round_rate(emi_intr_clk, lp_lpm_clk));
low_bus_freq_mode = 1;
high_bus_freq_mode = 0;
spin_unlock_irqrestore(&bus_freq_lock, flags);
/* Set the voltage to 1.05V for the LP domain. */
ret = regulator_set_voltage(lp_regulator, 1050000, 1050000);
udelay(100);
if (ret < 0) {
printk(KERN_ERR "COULD NOT SET LP VOLTAGE!!!!!!\n");
return ret;
}
return ret;
}
