void write_phy(uint8_t reg, uint16_t data)
{
switch_bank(2);
spi_transaction(WRITE_CONTROL_REGISTER, MIREGADR, reg);
spi_transaction(WRITE_CONTROL_REGISTER, MIWRL, data & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, MIWRH, (data>>8) & 0xFF);
switch_bank(3);
uint8_t read;
do {
read = spi_transaction(READ_CONTROL_REGISTER, MISTAT, 0);
} while(read & (1<<BUSY));
}
static void cmd_bfc(enc28j60_t *dev, uint8_t reg, int8_t bank, uint8_t mask)
{
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_BFC | reg, mask, 0);
gpio_set(dev->cs_pin);
}
static void cmd_wcr(enc28j60_t *dev, uint8_t reg, int8_t bank, uint8_t value)
{
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_WCR | reg, (char)value, 0);
gpio_set(dev->cs_pin);
}
void ethernet_initialize(uint8_t mac[6])
{
//Conf the LEDs
write_phy(PHLCON, 0b0011110000010011);
//Configure some buffers and MAC stuff for half duplex
//Recieve buffer spans 0x0000 to 0x0FFF
switch_bank(0);
spi_transaction(WRITE_CONTROL_REGISTER, ERXSTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXSTH, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXNDL, 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ERXNDH, 0x0F);
spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTH, 0x00);
//Transmit buffers covers 0x1000 to 0x1FFF
//...
uint8_t reg;
do {
reg = spi_transaction(READ_CONTROL_REGISTER, ESTAT, 0);
} while(!(reg & (1<<CLKRDY)));
//MAC settings
switch_bank(2);
spi_transaction(WRITE_CONTROL_REGISTER, MACON1, (1<<MARXEN));
spi_transaction(WRITE_CONTROL_REGISTER, MACON3, 0b11110000);
spi_transaction(WRITE_CONTROL_REGISTER, MACON4, 0b01000000); //DEFER
//1518 bytes
spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLL, 0xEE);
spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLH, 0x05);
spi_transaction(WRITE_CONTROL_REGISTER, MABBIPG, 0x12);
spi_transaction(WRITE_CONTROL_REGISTER, MAIPGL, 0x12);
spi_transaction(WRITE_CONTROL_REGISTER, MAIPGH, 0x0C);
set_mac(mac);
write_phy(PHCON2, (1<<HDLDIS));
write_phy(PHCON1, 0);
//Enable reception
spi_transaction(BIT_FIELD_SET, ECON1, (1<<RXEN));
puts("Enabled reception");
}
static uint8_t cmd_rcr(enc28j60_t *dev, uint8_t reg, int8_t bank)
{
char res;
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_RCR | reg, 0, &res);
gpio_set(dev->cs_pin);
return (uint8_t)res;
}
static uint8_t cmd_rcr_miimac(enc28j60_t *dev, uint8_t reg, int8_t bank)
{
char res[2];
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_regs(dev->spi, CMD_RCR | reg, NULL, res, 2);
gpio_set(dev->cs_pin);
return (uint8_t)res[1];
}
void set_mac(uint8_t mac[6])
{
switch_bank(3);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR1, mac[0]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR2, mac[1]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR3, mac[2]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR4, mac[3]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR5, mac[4]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR6, mac[5]);
}
void transmit_data(uint8_t * data, size_t len)
{
switch_bank(0);
spi_transaction(WRITE_CONTROL_REGISTER, ETXSTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ETXSTH, 0x10);
spi_transaction(WRITE_CONTROL_REGISTER, EWRPTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, EWRPTH, 0x10);
spi_transaction(WRITE_BUFFER_MEMORY, 0x1A, 0b00000000); //control byte
for(size_t i = 0; i < len; i++) {
spi_transaction(WRITE_BUFFER_MEMORY, 0x1A, data[i]);
}
uint16_t end = 0x1000 + len;
spi_transaction(WRITE_CONTROL_REGISTER, ETXNDL, end & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ETXNDH, (end>>8) & 0xFF);
spi_transaction(BIT_FIELD_SET, ECON1, (1<<TXRTS));
uint8_t reg;
do {
reg = spi_transaction(READ_CONTROL_REGISTER, ECON1, 0);
} while(reg & (1<<TXRTS));
reg = spi_transaction(READ_CONTROL_REGISTER, ESTAT, 0);
if(reg & (1<<TXABRT)) {
puts("Error occured during transmission");
}
if(reg & (1<<LATECOL)) {
puts("Late collision occured");
}
spi_transaction(WRITE_CONTROL_REGISTER, ERDPTL, (end+1) & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ERDPTH, ((end+1)>>8) & 0xFF);
for(int i = 0; i < 7; i++) {
printf("0x%02X ", spi_transaction(READ_BUFFER_MEMORY, 0x1A, 0));
}
puts("");
//}
}
static int w83977af_probe(int iobase, int irq, int dma)
{
int version;
int i;
for (i=0; i < 2; i++) {
IRDA_DEBUG( 0, "%s()\n", __func__ );
#ifdef CONFIG_USE_W977_PNP
/* Enter PnP configuration mode */
w977_efm_enter(efbase[i]);
w977_select_device(W977_DEVICE_IR, efbase[i]);
/* Configure PnP port, IRQ, and DMA channel */
w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
w977_write_reg(0x70, irq, efbase[i]);
#ifdef CONFIG_ARCH_NETWINDER
/* Netwinder uses 1 higher than Linux */
w977_write_reg(0x74, dma+1, efbase[i]);
#else
w977_write_reg(0x74, dma, efbase[i]);
#endif /*CONFIG_ARCH_NETWINDER */
w977_write_reg(0x75, 0x04, efbase[i]); /* Disable Tx DMA */
/* Set append hardware CRC, enable IR bank selection */
w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
/* Activate device */
w977_write_reg(0x30, 0x01, efbase[i]);
w977_efm_exit(efbase[i]);
#endif /* CONFIG_USE_W977_PNP */
/* Disable Advanced mode */
switch_bank(iobase, SET2);
outb(iobase+2, 0x00);
/* Turn on UART (global) interrupts */
switch_bank(iobase, SET0);
outb(HCR_EN_IRQ, iobase+HCR);
/* Switch to advanced mode */
switch_bank(iobase, SET2);
outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
/* Set default IR-mode */
switch_bank(iobase, SET0);
outb(HCR_SIR, iobase+HCR);
/* Read the Advanced IR ID */
switch_bank(iobase, SET3);
version = inb(iobase+AUID);
/* Should be 0x1? */
if (0x10 == (version & 0xf0)) {
efio = efbase[i];
/* Set FIFO size to 32 */
switch_bank(iobase, SET2);
outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
/* Set FIFO threshold to TX17, RX16 */
switch_bank(iobase, SET0);
outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
UFR_EN_FIFO,iobase+UFR);
/* Receiver frame length */
switch_bank(iobase, SET4);
outb(2048 & 0xff, iobase+6);
outb((2048 >> 8) & 0x1f, iobase+7);
/*
* Init HP HSDL-1100 transceiver.
*
* Set IRX_MSL since we have 2 * receive paths IRRX,
* and IRRXH. Clear IRSL0D since we want IRSL0 * to
* be a input pin used for IRRXH
*
* IRRX pin 37 connected to receiver
* IRTX pin 38 connected to transmitter
* FIRRX pin 39 connected to receiver (IRSL0)
* CIRRX pin 40 connected to pin 37
*/
switch_bank(iobase, SET7);
outb(0x40, iobase+7);
IRDA_MESSAGE("W83977AF (IR) driver loaded. "
"Version: 0x%02x\n", version);
return 0;
} else {
static int w83977af_probe(int iobase, int irq, int dma)
{
int version;
int i;
for (i=0; i < 2; i++) {
IRDA_DEBUG( 0, "%s()\n", __func__ );
#ifdef CONFIG_USE_W977_PNP
w977_efm_enter(efbase[i]);
w977_select_device(W977_DEVICE_IR, efbase[i]);
w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
w977_write_reg(0x70, irq, efbase[i]);
#ifdef CONFIG_ARCH_NETWINDER
w977_write_reg(0x74, dma+1, efbase[i]);
#else
w977_write_reg(0x74, dma, efbase[i]);
#endif
w977_write_reg(0x75, 0x04, efbase[i]);
w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
w977_write_reg(0x30, 0x01, efbase[i]);
w977_efm_exit(efbase[i]);
#endif
switch_bank(iobase, SET2);
outb(iobase+2, 0x00);
switch_bank(iobase, SET0);
outb(HCR_EN_IRQ, iobase+HCR);
switch_bank(iobase, SET2);
outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
switch_bank(iobase, SET0);
outb(HCR_SIR, iobase+HCR);
switch_bank(iobase, SET3);
version = inb(iobase+AUID);
if (0x10 == (version & 0xf0)) {
efio = efbase[i];
switch_bank(iobase, SET2);
outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
switch_bank(iobase, SET0);
outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
UFR_EN_FIFO,iobase+UFR);
switch_bank(iobase, SET4);
outb(2048 & 0xff, iobase+6);
outb((2048 >> 8) & 0x1f, iobase+7);
switch_bank(iobase, SET7);
outb(0x40, iobase+7);
IRDA_MESSAGE("W83977AF (IR) driver loaded. "
"Version: 0x%02x\n", version);
return 0;
} else {
int packets_available()
{
//Read EPKTCNT
switch_bank(1);
return(spi_transaction(READ_CONTROL_REGISTER, EPKTCNT, 0));
}
