static int __init stx7108_configure_miphy_uport(void) { struct sysconf_field *sc_miphy1_ref_clk, *sc_sata1_hc_reset, *sc_sata_pcie_sel, *sc_sata1_hc_srst; sc_pcie_mp_select = sysconf_claim(SYS_CFG_BANK4, 70, 0, 0, "pcie-mp"); BUG_ON(!sc_pcie_mp_select); /* SATA0_SOFT_RST_N_SATA: sata0_soft_rst_n_sata. */ /* Useless documentation R us */ sc_sata1_hc_srst = sysconf_claim(SYS_CFG_BANK4, 45, 4, 4, "MiPHY"); BUG_ON(!sc_sata1_hc_srst); /* SELECT_SATA: select_sata. */ sc_sata_pcie_sel = sysconf_claim(SYS_CFG_BANK4, 68, 1, 1, "MiPHY"); BUG_ON(!sc_sata_pcie_sel); /* SATAPHY1_OSC_FORCE_EXT: SATAphy1_osc_force_ext. */ sc_miphy1_ref_clk = sysconf_claim(SYS_CFG_BANK4, 68, 2, 2, "MiPHY"); BUG_ON(!sc_miphy1_ref_clk); /* RESETGEN_CONF0_1: Active low Software Reset for peripherals <31:0>. * NOTE documenation appears to be wrong! * RST_PER_N_30: SATA_2XHOST */ sc_sata1_hc_reset = sysconf_claim(SYS_CFG_BANK0, BANK0_REG(12), 30, 30, "SATA"); BUG_ON(!sc_sata1_hc_reset); /* Deassert Soft Reset to SATA0 */ sysconf_write(sc_sata1_hc_srst, 1); /* If the 100MHz xtal for PCIe is present, then the microport interface * will already have a clock, so there is no need to flip to the 30MHz * clock here. If it isn't then we have to switch miphy lane 1 to use * the 30MHz clock, as otherwise we will not be able to talk to lane 0 * since the uport interface itself is clocked from lane1 */ if (stx7108_miphy_modes[1] != PCIE_MODE) { /* Put MiPHY1 in reset - rst_per_n[32] */ sysconf_write(sc_miphy_reset[1], 0); /* Put SATA1 HC in reset - rst_per_n[30] */ sysconf_write(sc_sata1_hc_reset, 0); /* Now switch to Phy interface to SATA HC not PCIe HC */ sysconf_write(sc_sata_pcie_sel, 1); /* Select the Uport to use MiPHY1 */ stx7108_pcie_mp_select(1); /* Take SATA1 HC out of reset - rst_per_n[30] */ sysconf_write(sc_sata1_hc_reset, 1); /* MiPHY1 needs to be using the MiPHY0 reference clock */ sysconf_write(sc_miphy1_ref_clk, 1); /* Take MiPHY1 out of reset - rst_per_n[32] */ sysconf_write(sc_miphy_reset[1], 1); } stx7108_using_uport = 1; return platform_device_register(&stx7108_pcie_mp_device); }
static int __init suspend_platform_setup() { struct sysconf_field* sc; #ifdef CONFIG_PM_DEBUG /* route the sh4/2 clock frequenfy */ iowrite32(0xc, CLOCKGENA_BASE_ADDR + CKGA_CLKOBS_MUX1_CFG); #endif sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm"); stx7111_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc); stx7111_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_CFG, 11, 12, 12, "pm"); stx7111_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc); stx7111_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm"); stx7111_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc); stx7111_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_STA, 3, 0, 0, "pm"); stx7111_wrt_table[_SYS_STA3] = (unsigned long)sysconf_address(sc); stx7111_wrt_table[_SYS_STA3_MASK] = sysconf_mask(sc); stx7111_wrt_table[_SYS_STA3_VALUE] = 0; return sh4_suspend_register(&st40data); }
static int __init fli7510_suspend_setup(void) { struct sysconf_field *sc[2]; int i; sc[0] = sysconf_claim(CKG_DDR_CTL_PLL_DDR_FREQ, 0, 0, "PM"); sc[1] = sysconf_claim(CKG_DDR_STATUS_PLL_DDR, 0, 0, "PM"); for (i = ARRAY_SIZE(sc)-1; i; --i) if (!sc[i]) goto error; cga = ioremap(CGA, 0x1000); ca_ic_100_clk = clk_get(NULL, "comms_clk"); ca_pll_clk = ca_ic_100_clk->parent; ca_ref_clk = ca_pll_clk->parent; return stm_suspend_register(&fli7510_suspend); error: for (i = ARRAY_SIZE(sc)-1; i; --i) if (sc[i]) sysconf_release(sc[i]); pr_err("[STM][PM] Error on Standby initialization\n"); return 0; }
void __init stx7108_configure_miphy(struct stx7108_miphy_config *config) { int err = 0; memcpy(stx7108_miphy_modes, config->modes, sizeof(stx7108_miphy_modes)); /* RESETGEN_CONF0_1: Active low Software Reset for peripherals <31:0>. * NOTE documenation appears to be wrong! * RST_PER_N_31: SATA PHI 0 */ sc_miphy_reset[0] = sysconf_claim(SYS_CFG_BANK0, BANK0_REG(12), 31, 31, "SATA"); BUG_ON(!sc_miphy_reset[0]); /* RESETGEN_CONF0_2: Active low Software Reset for peripherals <63:32>. * NOTE documenation appears to be wrong! * RST_PER_N_32: SATA PHI 1 */ sc_miphy_reset[1] = sysconf_claim(SYS_CFG_BANK0, BANK0_REG(13), 0, 0, "SATA"); BUG_ON(!sc_miphy_reset[1]); if (cpu_data->cut_major >= 2 && !config->force_jtag) err = stx7108_configure_miphy_uport(); else err = stx7108_configure_miphy_tap(); }
static int __init stih415_configure_miphy_uport(void) { struct sysconf_field *sc_miphy1_ref_clk, *sc_sata1_hc_reset, *sc_sata_pcie_sel, *sc_sata0_hc_reset; sc_pcie_mp_select = sysconf_claim(SYSCONF(335), 0, 0, "pcie-mp"); BUG_ON(!sc_pcie_mp_select); /* SATA0_SOFT_RST_N_SATA: sata0_soft_rst_n_sata. */ sc_sata0_hc_reset = sysconf_claim(SYSCONF(377), 7, 7, "MiPHY"); BUG_ON(!sc_sata0_hc_reset); /* SELECT_SATA: select_sata. */ sc_sata_pcie_sel = sysconf_claim(SYSCONF(333), 1, 1, "MiPHY"); BUG_ON(!sc_sata_pcie_sel); /* SATAPHY1_OSC_FORCE_EXT: SATAphy1_osc_force_ext. */ sc_miphy1_ref_clk = sysconf_claim(SYSCONF(333), 2, 2, "MiPHY"); BUG_ON(!sc_miphy1_ref_clk); /*SATA1_SOFT_RST_N_SATA: sata1_soft_rst_n_sata */ sc_sata1_hc_reset = sysconf_claim(SYSCONF(377), 3, 3, "SATA"); BUG_ON(!sc_sata1_hc_reset); /* Deassert Soft Reset to SATA0 */ sysconf_write(sc_sata0_hc_reset, 1); /* If the 100MHz xtal for PCIe is present, then the microport interface * will already have a clock, so there is no need to flip to the 30MHz * clock here. If it isn't then we have to switch miphy lane 1 to use * the 30MHz clock, as otherwise we will not be able to talk to lane 0 * since the uport interface itself is clocked from lane1 */ if (stih415_miphy_modes[1] != PCIE_MODE) { /* Put MiPHY1 in reset - rst_per_n[32] */ sysconf_write(sc_miphy_reset[1], 0); /* Put SATA1 HC in reset - rst_per_n[30] */ sysconf_write(sc_sata1_hc_reset, 0); /* Now switch to Phy interface to SATA HC not PCIe HC */ sysconf_write(sc_sata_pcie_sel, 1); /* Select the Uport to use MiPHY1 */ stih415_pcie_mp_select(1); /* Take SATA1 HC out of reset - rst_per_n[30] */ sysconf_write(sc_sata1_hc_reset, 1); /* MiPHY1 needs to be using the MiPHY0 reference clock */ sysconf_write(sc_miphy1_ref_clk, 1); /* Take MiPHY1 out of reset - rst_per_n[32] */ sysconf_write(sc_miphy_reset[1], 1); } return platform_device_register(&stih415_pcie_mp_device); }
void __init stih415_configure_miphy(struct stih415_miphy_config *config) { int err = 0; memcpy(stih415_miphy_modes, config->modes, sizeof(stih415_miphy_modes)); /*Reset to MIPHY0 */ sc_miphy_reset[0] = sysconf_claim(SYSCONF(376), 18, 18, "SATA"); BUG_ON(!sc_miphy_reset[0]); /* Reset to MIPHY1 */ sc_miphy_reset[1] = sysconf_claim(SYSCONF(376), 19, 19, "SATA"); BUG_ON(!sc_miphy_reset[1]); err = stih415_configure_miphy_uport(); }
static int usb_pwr_dwn(struct platform_device *dev, int host_phy, int pwd) { static struct sysconf_field *sc, *sc_clk; /* Power on USB */ if (!sc) { sc = sysconf_claim(SYS_CFG, 32, 4, 4, "USB_PW_REQ"); sc_clk = sysconf_claim(SYS_CFG, 40, 2, 3, "usb_clk"); } sysconf_write(sc, (pwd ? 1 : 0)); sysconf_write(sc_clk, (pwd ? 3 : 0)); return 0; }
int __init stmcore_probe_device(struct stmcore_display_pipeline_data **pd, int *nr_platform_devices) { if(boot_cpu_data.type == CPU_STX7106) { *pd = platform_data; *nr_platform_devices = N_ELEMENTS (platform_data); /* * Setup HDMI hotplug */ hotplug_pio = stpio_request_pin(9,7,"HDMI Hotplug",STPIO_IN); if (hotplug_pio) { /* enable hotplug pio in syscfg */ syscfg2_27 = sysconf_claim (SYS_CFG, 2, 27, 27, "HDMI Hotplug PIO enable"); sysconf_write (syscfg2_27, 1); printk (KERN_INFO "stmcore-display: using HDMI hotplug\n"); } else printk (KERN_INFO "stmcore-display: HDMI hotplug not available\n"); printk(KERN_WARNING "stmcore-display: STi7106 display: probed\n"); return 0; } printk(KERN_WARNING "stmcore-display: STi7106 display: platform unknown\n"); return -ENODEV; }
int __init stmcore_probe_device(struct stmcore_display_pipeline_data **pd, int *nr_platform_devices) { if(boot_cpu_data.type == CPU_STX7141) { unsigned long syscfg20; *pd = platform_data; *nr_platform_devices = N_ELEMENTS (platform_data); /* * Setup HDMI hotplug */ hotplug_pio = stpio_request_pin(5,6,"HDMI Hotplug",STPIO_IN); /* * Enable hotplug pio in syscfg */ syscfg20_24 = sysconf_claim(SYS_CFG,20,24,24,"HDMI Hotplug PIO ALT Function"); sysconf_write(syscfg20_24,1); printk(KERN_WARNING "stmcore-display: STi7141 display probed\n"); return 0; } printk(KERN_WARNING "stmcore-display: STi7141 display not found\n"); return -ENODEV; }
void __init stx7106_configure_spifsm(struct stm_plat_spifsm_data *data) { struct sysconf_field *sc; /* Not available on stx7105 */ BUG_ON(cpu_data->type == CPU_STX7105); stx7106_spifsm_device.dev.platform_data = data; sc = sysconf_claim(SYS_STA, 1, 5, 8, "boot-device"); /* SoC/IP Capabilities */ data->capabilities.quad_mode = 0; data->capabilities.no_write_repeat = 1; data->capabilities.read_status_bug = spifsm_no_read_status; data->capabilities.boot_from_spi = (sysconf_read(sc) == 0xa) ? 1 : 0; /* Dual mode not possible due to pad configurations issues */ data->capabilities.dual_mode = 0; data->pads = &stx7106_spifsm_pad_config; if (cpu_data->cut_major == 1) { data->capabilities.no_clk_div_4 = 1; data->capabilities.dummy_on_write = 1; data->capabilities.no_sw_reset = 1; } else if (cpu_data->cut_major == 3) { data->capabilities.no_poll_mode_change = 1; } sysconf_release(sc); platform_device_register(&stx7106_spifsm_device); }
int __init device_init_stb840_promSvyaz(int ver) { struct sysconf_field *sc; stx7105_configure_sata(0); /* Set SPI Boot pads as inputs to avoid contention with SSC1 */ gpio_request(stm_gpio(15, 0), "SPI Boot CLK"); gpio_direction_input(stm_gpio(15, 0)); gpio_request(stm_gpio(15, 1), "SPI Boot DOUT"); gpio_direction_input(stm_gpio(15, 1)); gpio_request(stm_gpio(15, 2), "SPI Boot NOTCS"); gpio_direction_input(stm_gpio(15, 2)); gpio_request(stm_gpio(15, 3), "SPI Boot DIN"); gpio_direction_input(stm_gpio(15, 3)); /* * Fix the reset chain so it correct to start with in case the * watchdog expires or we trigger a reset. */ sc = sysconf_claim(SYS_CFG, 9, 27, 28, "reset_chain"); sysconf_write(sc, 0); /* Release the sysconf bits so the coprocessor driver can claim them */ sysconf_release(sc); /* I2C_xxxA - HDMI */ stx7105_configure_ssc_i2c(0, &(struct stx7105_ssc_config) { .routing.ssc0.sclk = stx7105_ssc0_sclk_pio2_2, .routing.ssc0.mtsr = stx7105_ssc0_mtsr_pio2_3, });
/* STiH205 has 1 × eSATA or 1 × PCI-express, and can be configured * to map PCIe, instead of eSATA, on PHY Lane */ void __init stxh205_configure_miphy(struct stxh205_miphy_config *config) { struct sysconf_field *sel_sata; if (config->iface != UPORT_IF) { printk(KERN_ERR "MiPhy only supported in microport mode\n"); return; } sel_sata = sysconf_claim(SYSCONF(445), 1, 1, "sata/pcie"); if (!sel_sata) { printk(KERN_ERR "Cannot claim SELECT_SATA sysconf\n"); return; } stxh205_miphy_modes[0] = config->mode; stxh205_pcie_mp_platform_data.rx_pol_inv = config->rx_pol_inv; stxh205_pcie_mp_platform_data.tx_pol_inv = config->tx_pol_inv; /* Select either PCIE or SATA mode */ sysconf_write(sel_sata, config->mode == SATA_MODE); if (config->mode == PCIE_MODE) { struct sysconf_field *miphy_reset, *pcie_reset, *pcie_clk_sel; /* Change addresses to other port */ stxh205_pcie_mp_device.resource[0].start = PCIE_UPORT_BASE, stxh205_pcie_mp_device.resource[0].end = PCIE_UPORT_BASE + UPORT_REG_SIZE; miphy_reset = sysconf_claim(SYSCONF(460), 18, 18, "miphy"); pcie_reset = sysconf_claim(SYSCONF(461), 0, 0, "pcie"); pcie_clk_sel = sysconf_claim(SYSCONF(468), 0, 0, "pcie"); sysconf_write(miphy_reset, 0); /* Reset miphy */ sysconf_write(pcie_reset, 0); /* Reset PCIe */ sysconf_write(pcie_clk_sel, 1); /* Select 100MHz ext clock */ sysconf_write(miphy_reset, 1); /* Release miphy */ sysconf_write(pcie_reset, 1); /* Release PCIe */ } platform_device_register(&stxh205_pcie_mp_device); }
int stih415_gmac0_claim(struct stm_pad_state *state, void *priv) { gbit_sc[0] = sysconf_claim(SYSCONF(382), 6, 8, "gmac-0"); if (!gbit_sc[0]) return -1; sysconf_write(gbit_sc[0], 0); return 0; }
int stih415_gmac1_claim(struct stm_pad_state *state, void *priv) { gbit_sc[1] = sysconf_claim(SYSCONF(29), 6, 8, "gmac-1"); if (!gbit_sc[1]) return -1; sysconf_write(gbit_sc[1], 0); return 0; }
static int emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn) { static struct sysconf_field *sc; if (!sc) sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr"); sysconf_write(sc, (dwn ? 1 : 0)); return 0; }
static int __init stxh205_suspend_setup(void) { struct sysconf_field *sc[2]; int i; sc[0] = sysconf_claim(SYSCONF(169), 2, 2, "PM"); /* ClockGen_D.Pll lock status */ sc[1] = sysconf_claim(SYSCONF(154), 2, 2, "PM"); for (i = 0; i < ARRAY_SIZE(sc); ++i) if (!sc[i]) goto error; a0_ic_lp_on_clk = clk_get(NULL, "CLK_A0_IC_REG_LP_ON"); a0_ref_clk = clk_get(NULL, "CLK_A0_REF"); a1_pll0_hs_clk = clk_get(NULL, "CLK_A1_PLL0HS"); a1_ddr_clk = clk_get(NULL, "CLK_A1_IC_DDRCTRL"); a1_pll1_ls_clk = clk_get(NULL, "CLK_A1_PLL1LS"); a1_eth_phy_clk = clk_get(NULL, "CLK_A1_ETH_PHY"); if (a0_ref_clk == ERR_PTR(-ENOENT) || a0_ic_lp_on_clk == ERR_PTR(-ENOENT) || a1_pll0_hs_clk == ERR_PTR(-ENOENT) || a1_pll0_hs_clk == ERR_PTR(-ENOENT) || a1_pll1_ls_clk == ERR_PTR(-ENOENT) || a1_eth_phy_clk == ERR_PTR(-ENOENT)) goto error; cga0 = ioremap_nocache(0xfde98000, 0x1000); cga1 = ioremap_nocache(0xfdab8000, 0x1000); return stm_suspend_register(&stxh205_suspend); error: pr_err("[STM][PM] Error to acquire the sysconf registers\n"); for (i = 0; i < ARRAY_SIZE(sc); ++i) if (sc[i]) sysconf_release(sc[i]); return -EBUSY; }
static int usb_pm_pwd_dwn(struct platform_device *dev, int host_phy, int pwd) { static struct sysconf_field *sc; if(!sc) sc = sysconf_claim(SYS_CFG, 2, 4, 5, "usb rx/tx"); sysconf_write(sc, (pwd ? 0 : 3)); return 0; }
void __init stx7100_configure_ethernet(struct stx7100_ethernet_config *config) { static int configured; struct stx7100_ethernet_config default_config; struct stm_pad_config *pad_config; int interface; /* 7100 doesn't have a MAC */ if (cpu_data->type == CPU_STX7100) return; BUG_ON(configured); configured = 1; if (!config) config = &default_config; pad_config = &stx7100_ethernet_pad_configs[config->mode]; switch (config->mode) { case stx7100_ethernet_mode_mii: if (config->ext_clk) stm_pad_set_pio_ignored(pad_config, "PHYCLK"); interface = PHY_INTERFACE_MODE_MII; break; case stx7100_ethernet_mode_rmii: if (config->ext_clk) stm_pad_set_pio_in(pad_config, "PHYCLK", -1); interface = PHY_INTERFACE_MODE_RMII; break; default: BUG(); break; } pad_config->sysconfs[2].value = (config->ext_clk ? 1 : 0); stx7100_ethernet_platform_data.custom_cfg = (void *) pad_config; stx7100_ethernet_platform_data.interface = interface; stx7100_ethernet_platform_data.bus_id = config->phy_bus; stx7100_ethernet_platform_data.phy_addr = config->phy_addr; stx7100_ethernet_platform_data.mdio_bus_data = config->mdio_bus_data; /* MAC_SPEED_SEL */ stx7100_ethernet_platform_data.bsp_priv = sysconf_claim(SYS_CFG, 7, 20, 20, "stmmac"); /* Configure the ethernet MAC PBL depending on the cut of the chip */ /*stx7100_ethernet_platform_data.pbl = (cpu_data->cut_major == 1) ? 1 : 32;*/ platform_device_register(&stx7100_ethernet_device); }
static int __init suspend_platform_setup(void) { struct sysconf_field* sc; sc = sysconf_claim(SYS_CFG, 38, 20, 20, "pm"); stx7105_wrt_table[_SYS_CFG38] = (unsigned long)sysconf_address(sc); stx7105_wrt_table[_SYS_CFG38_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_CFG, 11, 12, 12, "pm"); stx7105_wrt_table[_SYS_CFG11] = (unsigned long)sysconf_address(sc); stx7105_wrt_table[_SYS_CFG11_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_STA, 4, 0, 0, "pm"); stx7105_wrt_table[_SYS_STA4] = (unsigned long)sysconf_address(sc); stx7105_wrt_table[_SYS_STA4_MASK] = sysconf_mask(sc); sc = sysconf_claim(SYS_STA, 3, 0, 0, "pm"); stx7105_wrt_table[_SYS_STA3] = (unsigned long)sysconf_address(sc); stx7105_wrt_table[_SYS_STA3_MASK] = sysconf_mask(sc); stx7105_wrt_table[_SYS_STA3_VALUE] = 0; return sh4_suspend_register(&st40data); }
static int usb_pwr_dwn(struct platform_device *pdev, int host_phy, int pwd) { static struct sysconf_field *sc[3]; int port = pdev->id; /* Power up port */ if (!sc[port]) sc[port] = sysconf_claim(SYS_CFG, 22, 3+port, 3+port, "usb pwr"); sysconf_write(sc[port], (pwd ? 1 : 0)); return 0; }
static int sata_pwd_dwn_req(struct platform_device *pdev, int host_phy, int pwd) { static struct sysconf_field *sc[2]; if (cpu_data->cut_major < 3) return 0; if (!sc[pdev->id]) sc[pdev->id] = sysconf_claim(SYS_CFG, 22, 1 + pdev->id, 1 + pdev->id, "sata"); sysconf_write(sc[pdev->id], (pwd ? 1 : 0)); return 0; }
static int emi_pwr_dwn_ack(struct platform_device *dev, int host_phy, int ack) { static struct sysconf_field *sc; int i; if (!sc) sc = sysconf_claim(SYS_STA, 15, 1, 1, "emi pwr ack"); for (i = 5; i; --i) { if (sysconf_read(sc) == ack) return 0; mdelay(10); } return -EINVAL; }
static int usb_sw_reset(struct platform_device *dev, int host_phy) { static struct sysconf_field *sc; /* Reset USB */ if (!sc) sc = sysconf_claim(SYS_CFG, 4, 4, 4, "USB_RST"); sysconf_write(sc, 0); mdelay(10); sysconf_write(sc, 1); mdelay(10); return 0; }
static int usb_pwr_ack(struct platform_device *dev, int host_phy, int on) { static struct sysconf_field *sc; int i; if (!sc) sc = sysconf_claim(SYS_STA, 15, 4, 4, "USB_PW_ACK"); for (i = 5; i; --i) { if (sysconf_read(sc) == on) return 0; mdelay(10); } return -EINVAL; }
static int usb_pm_sw_reset(struct platform_device *dev) { static struct sysconf_field *sc; unsigned long reg; if (!sc) sc = sysconf_claim(SYS_CFG, 2, 1, 1, "usb reset"); reg = sysconf_read(sc); if (reg) { sysconf_write(sc, 0); mdelay(30); } return 0; }
static int usb_pwr_ack(struct platform_device *pdev, int host_phy, int ack) { static struct sysconf_field *sc[3]; int port = pdev->id; int i; if (!sc[port]) sc[port] = sysconf_claim(SYS_STA, 13, 2+port, 2+port, "usb ack"); for (i = 5; i; --i) { if (sysconf_read(sc[port]) == ack) return 0; mdelay(10); } return -EINVAL; }
void __init stxh205_configure_pcie(struct stxh205_pcie_config *config) { struct sysconf_field *sc; sc = sysconf_claim(SYSCONF(447), 0, 5, "pcie"); BUG_ON(!sc); stxh205_plat_pcie_config.ops_handle = sc; stxh205_plat_pcie_config.reset_gpio = config->reset_gpio; stxh205_plat_pcie_config.reset = config->reset; /* There is only one PCIe controller on the stxh205 */ stxh205_plat_pcie_config.miphy_num = 0; platform_device_register(&stxh205_pcie_device); }
static int sata_pwd_dwn_ack(struct platform_device *pdev, int host_phy, int ack) { static struct sysconf_field *sc[2]; int i; if (cpu_data->cut_major < 3) return 0; if (!sc[pdev->id]) sc[pdev->id] = sysconf_claim(SYS_STA, 13, 0 + pdev->id, 0 + pdev->id, "sata"); for (i = 5; i; --i) { if (sysconf_read(sc[pdev->id]) == ack) return 0; mdelay(10); } return -EINVAL; }
void __init stx7108_configure_pcie(struct stx7108_pcie_config *config) { struct sysconf_field *sc; sc = sysconf_claim(SYS_CFG_BANK4, 69, 0, 6, "pcie"); BUG_ON(!sc); stx7108_plat_pcie_config.ops_handle = sc; stx7108_plat_pcie_config.reset_gpio = config->reset_gpio; stx7108_plat_pcie_config.reset = config->reset; /* There is only one PCIe controller on the 7108c2 and it is hardwired * to use lane1 */ stx7108_plat_pcie_config.miphy_num = 1; platform_device_register(&stx7108_pcie_device); }
void __init stx7108_configure_usb(int port) { static int osc_initialized; static int configured[ARRAY_SIZE(stx7108_usb_devices)]; struct sysconf_field *sc; BUG_ON(port < 0 || port >= ARRAY_SIZE(stx7108_usb_devices)); BUG_ON(configured[port]++); if (!osc_initialized++) { /* USB2TRIPPHY_OSCIOK */ sc = sysconf_claim(SYS_CFG_BANK4, 44, 6, 6, "USB"); sysconf_write(sc, 1); } platform_device_register(&stx7108_usb_devices[port]); }