static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) { int bus_speed = system_bus_clock(); if (dev->resource[PCI_ROM_RESOURCE].start) { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start); } #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS) aec_devs[n_aec_devs++] = dev; if (!aec62xx_proc) { aec62xx_proc = 1; ide_pci_create_host_proc("aec62xx", aec62xx_get_info); } #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */ if (bus_speed <= 33) pci_set_drvdata(dev, (void *) aec6xxx_33_base); else pci_set_drvdata(dev, (void *) aec6xxx_34_base); return dev->irq; }
static void compute_clocks(int pio, pio_clocks_t *clks) { if (pio != PIO_NOT_EXIST) { int adr_setup, data_pls; int bus_speed = system_bus_clock(); adr_setup = ide_pio_timings[pio].setup_time; data_pls = ide_pio_timings[pio].active_time; clks->address_time = cmpt_clk(adr_setup, bus_speed); clks->data_time = cmpt_clk(data_pls, bus_speed); clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time - adr_setup-data_pls, bus_speed); if (clks->address_time<1) clks->address_time = 1; if (clks->address_time>4) clks->address_time = 4; if (clks->data_time<1) clks->data_time = 1; if (clks->data_time>16) clks->data_time = 16; if (clks->recovery_time<2) clks->recovery_time = 2; if (clks->recovery_time>17) clks->recovery_time = 17; } else { clks->address_time = 1; clks->data_time = 1; clks->recovery_time = 2; /* minimal values */ } }
/* * Set PIO mode for the specified drive. * This function computes timing parameters * and sets controller registers accordingly. */ static void ali14xx_tune_drive (ide_drive_t *drive, u8 pio) { int driveNum; int time1, time2; u8 param1, param2, param3, param4; unsigned long flags; ide_pio_data_t d; int bus_speed = system_bus_clock(); pio = ide_get_best_pio_mode(drive, pio, ALI_MAX_PIO, &d); /* calculate timing, according to PIO mode */ time1 = d.cycle_time; time2 = ide_pio_timings[pio].active_time; param3 = param1 = (time2 * bus_speed + 999) / 1000; param4 = param2 = (time1 * bus_speed + 999) / 1000 - param1; if (pio < 3) { param3 += 8; param4 += 8; } printk(KERN_DEBUG "%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n", drive->name, pio, time1, time2, param1, param2, param3, param4); /* stuff timing parameters into controller registers */ driveNum = (HWIF(drive)->index << 1) + drive->select.b.unit; spin_lock_irqsave(&ide_lock, flags); outb_p(regOn, basePort); outReg(param1, regTab[driveNum].reg1); outReg(param2, regTab[driveNum].reg2); outReg(param3, regTab[driveNum].reg3); outReg(param4, regTab[driveNum].reg4); outb_p(regOff, basePort); spin_unlock_irqrestore(&ide_lock, flags); }
static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) { int bus_speed = system_bus_clock(); if (dev->resource[PCI_ROM_RESOURCE].start) { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, (unsigned long)dev->resource[PCI_ROM_RESOURCE].start); } if (bus_speed <= 33) pci_set_drvdata(dev, (void *) aec6xxx_33_base); else pci_set_drvdata(dev, (void *) aec6xxx_34_base); /* These are necessary to get AEC6280 Macintosh cards to work */ if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) || (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) { u8 reg49h = 0, reg4ah = 0; /* Clear reset and test bits. */ pci_read_config_byte(dev, 0x49, ®49h); pci_write_config_byte(dev, 0x49, reg49h & ~0x30); /* Enable chip interrupt output. */ pci_read_config_byte(dev, 0x4a, ®4ah); pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01); /* Enable burst mode. */ pci_read_config_byte(dev, 0x4a, ®4ah); pci_write_config_byte(dev, 0x4a, reg4ah | 0x80); } return dev->irq; }
static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio) { ide_hwif_t *hwif = HWIF(drive); struct pci_dev *dev = to_pci_dev(hwif->dev); int s_time, a_time, c_time; u8 s_clc, a_clc, r_clc; unsigned long flags; int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock(); int port = hwif->channel ? 0x5c : 0x58; int portFIFO = hwif->channel ? 0x55 : 0x54; u8 cd_dma_fifo = 0; int unit = drive->select.b.unit & 1; s_time = ide_pio_timings[pio].setup_time; a_time = ide_pio_timings[pio].active_time; if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8) s_clc = 0; if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8) a_clc = 0; c_time = ide_pio_timings[pio].cycle_time; if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) { r_clc = 1; } else { if (r_clc >= 16) r_clc = 0; } local_irq_save(flags); /* * PIO mode => ATA FIFO on, ATAPI FIFO off */ pci_read_config_byte(dev, portFIFO, &cd_dma_fifo); if (drive->media==ide_disk) { if (unit) { pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50); } else { pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05); } } else { if (unit) { pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F); } else { pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0); } } pci_write_config_byte(dev, port, s_clc); pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc); local_irq_restore(flags); }
static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) { int bus_speed = system_bus_clock(); if (dev->resource[PCI_ROM_RESOURCE].start) { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start); } if (bus_speed <= 33) pci_set_drvdata(dev, (void *) aec6xxx_33_base); else pci_set_drvdata(dev, (void *) aec6xxx_34_base); return dev->irq; }
static u8 ht_pio2timings(ide_drive_t *drive, const u8 pio) { int active_time, recovery_time; int active_cycles, recovery_cycles; int bus_speed = system_bus_clock(); if (pio) { unsigned int cycle_time; cycle_time = ide_pio_cycle_time(drive, pio); /* * Just like opti621.c we try to calculate the * actual cycle time for recovery and activity * according system bus speed. */ active_time = ide_pio_timings[pio].active_time; recovery_time = cycle_time - active_time - ide_pio_timings[pio].setup_time; /* * Cycle times should be Vesa bus cycles */ active_cycles = (active_time * bus_speed + 999) / 1000; recovery_cycles = (recovery_time * bus_speed + 999) / 1000; /* * Upper and lower limits */ if (active_cycles < 2) active_cycles = 2; if (recovery_cycles < 2) recovery_cycles = 2; if (active_cycles > 15) active_cycles = 15; if (recovery_cycles > 15) recovery_cycles = 0; /* 0==16 */ #ifdef DEBUG printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d (%dns)\n", drive->name, pio, recovery_cycles, recovery_time, active_cycles, active_time); #endif return (u8)((recovery_cycles << 4) | active_cycles); } else { #ifdef DEBUG printk("ht6560b: drive %s setting pio=0\n", drive->name); #endif return HT_TIMING_DEFAULT; /* default setting */ } }
static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted) { int setup_time, active_time, recovery_time; int clock_time, pio_mode, cycle_time; u8 recovery_count2, cycle_count; int setup_count, active_count, recovery_count; int bus_speed = system_bus_clock(); /*byte b;*/ ide_pio_data_t d; switch (mode_wanted) { case 8: /* set prefetch off */ case 9: /* set prefetch on */ mode_wanted &= 1; /*set_prefetch_mode(index, mode_wanted);*/ cmdprintk("%s: %sabled cmd640 prefetch\n", drive->name, mode_wanted ? "en" : "dis"); return; } mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d); pio_mode = d.pio_mode; cycle_time = d.cycle_time; /* * I copied all this complicated stuff from cmd640.c and made a few * minor changes. For now I am just going to pray that it is correct. */ if (pio_mode > 5) pio_mode = 5; setup_time = ide_pio_timings[pio_mode].setup_time; active_time = ide_pio_timings[pio_mode].active_time; recovery_time = cycle_time - (setup_time + active_time); clock_time = 1000 / bus_speed; cycle_count = (cycle_time + clock_time - 1) / clock_time; setup_count = (setup_time + clock_time - 1) / clock_time; active_count = (active_time + clock_time - 1) / clock_time; recovery_count = (recovery_time + clock_time - 1) / clock_time; recovery_count2 = cycle_count - (setup_count + active_count); if (recovery_count2 > recovery_count) recovery_count = recovery_count2; if (recovery_count > 16) { active_count += recovery_count - 16; recovery_count = 16; } if (active_count > 16) active_count = 16; /* maximum allowed by cmd646 */ /* * In a perfect world, we might set the drive pio mode here * (using WIN_SETFEATURE) before continuing. * * But we do not, because: * 1) this is the wrong place to do it * (proper is do_special() in ide.c) * 2) in practice this is rarely, if ever, necessary */ program_drive_counts (drive, setup_count, active_count, recovery_count); cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, " "clocks=%d/%d/%d\n", drive->name, pio_mode, mode_wanted, cycle_time, d.overridden ? " (overriding vendor mode)" : "", setup_count, active_count, recovery_count); }
static unsigned int __init init_chipset_aec62xx (struct pci_dev *dev, const char *name) { int bus_speed = system_bus_clock(); #ifndef CONFIG_BCM947XX if (dev->resource[PCI_ROM_RESOURCE].start) { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start); } #else if (dev->resource[PCI_ROM_RESOURCE].start) { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE]. start | PCI_ROM_ADDRESS_ENABLE); } else { pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE]. start); } /* Set IDE controller parameters manually - FIXME: replace magic values */ { byte setting; pci_write_config_word(dev, PCI_COMMAND, 0x0007); //pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13); pci_write_config_byte(dev, 0x40, 0x31); pci_write_config_byte(dev, 0x41, 0x31); pci_write_config_byte(dev, 0x42, 0x31); pci_write_config_byte(dev, 0x43, 0x31); // Set IDE Command Speed pci_write_config_byte(dev, 0x48, 0x31); // Disable WriteSubSysID & PIOROM pci_read_config_byte(dev, 0x49, &setting); setting &= 0x07; pci_write_config_byte(dev, 0x49, setting); // Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80 pci_read_config_byte(dev, 0x4A, &setting); //setting = (setting & 0xFE) | 0xA8; setting = (setting & 0xFE) | 0xD8; setting = (setting & 0xF7); pci_write_config_byte(dev, 0x4A, setting); //pci_write_config_byte(dev, 0x4B, 0x20); pci_write_config_byte(dev, 0x4B, 0x2C); //pci_write_config_byte(dev, 0x4B, 0x0C); // Set PreRead count: 512 byte pci_write_config_byte(dev, 0x4C, 0); pci_write_config_word(dev, 0x4D, 0x0002); pci_write_config_byte(dev, 0x54, 0); pci_write_config_word(dev, 0x55, 0x0002); } #endif #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS) aec_devs[n_aec_devs++] = dev; if (!aec62xx_proc) { aec62xx_proc = 1; ide_pci_register_host_proc(&aec62xx_procs[0]); } #endif /* DISPLAY_AEC62XX_TIMINGS && CONFIG_PROC_FS */ if (bus_speed <= 33) pci_set_drvdata(dev, (void *) aec6xxx_33_base); else pci_set_drvdata(dev, (void *) aec6xxx_34_base); return dev->irq; }