int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
mdp_clock_disable(dual_dsi);
}
return NO_ERROR;
}
int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret;
dprintf(SPEW, "%s: target_panel_clock\n", __func__);
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(0);
return ret;
}
edp_clk_enable();
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
edp_clk_disable();
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
void mipi_dsi_shutdown(void)
{
if(!target_cont_splash_screen())
{
mdp_shutdown();
writel(0x01010101, DSI_INT_CTRL);
writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
#if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \
|| DISPLAY_MIPI_PANEL_TOSHIBA)
secure_writel(0x0, DSI_CC_REG);
secure_writel(0x0, DSI_PIXEL_CC_REG);
#endif
writel(0, DSI_CLK_CTRL);
writel(0, DSI_CTRL);
writel(0, DSIPHY_PLL_CTRL(0));
}
else
{
/* To keep the splash screen displayed till kernel driver takes
control, do not turn off the video mode engine and clocks.
Only disabling the MIPI DSI IRQs */
writel(0x01010101, DSI_INT_CTRL);
writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
}
}
int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret = NO_ERROR;
uint32_t ldocounter = 0;
uint32_t pm8x41_ldo_base = 0x13F00;
while (ldocounter < TOTAL_LDO_DEFINED) {
struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
0x100 * ldo_entry_array[ldocounter].ldo_id),
ldo_entry_array[ldocounter].ldo_type);
dprintf(SPEW, "Setting %d\n",
ldo_entry_array[ldocounter].ldo_id);
/* Set voltage during power on */
if (enable) {
pm8x41_ldo_set_voltage(&ldo_entry,
ldo_entry_array[ldocounter].ldo_voltage);
pm8x41_ldo_control(&ldo_entry, enable);
} else if(!target_cont_splash_screen() &&
ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
pm8x41_ldo_control(&ldo_entry, enable);
}
ldocounter++;
}
return ret;
}
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
if (enable) {
if (pinfo->mipi.use_enable_gpio) {
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength,
enable_gpio.pin_state);
gpio_set_dir(enable_gpio.pin_id, 2);
}
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
gpio_set_dir(reset_gpio.pin_id, 2);
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]);
mdelay(resetseq->sleep[0]);
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]);
mdelay(resetseq->sleep[1]);
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]);
mdelay(resetseq->sleep[2]);
} else if(!target_cont_splash_screen()) {
gpio_set_value(reset_gpio.pin_id, 0);
if (pinfo->mipi.use_enable_gpio)
gpio_set_value(enable_gpio.pin_id, 0);
}
return ret;
}
int mdp_dma_off()
{
int ret = 0;
if (!target_cont_splash_screen())
writel(0x00000000, MDP_DMA_P_START);
return ret;
}
int mdp_dsi_video_off(void)
{
if (!target_cont_splash_screen()) {
mdp_disable();
mdelay(60);
}
writel(0x00000000, MDP_INTR_ENABLE);
writel(0x01ffffff, MDP_INTR_CLEAR);
return NO_ERROR;
}
static int fusion3_mtp_clock(int enable)
{
if (enable) {
mdp_clock_init();
mmss_clock_init();
} else if(!target_cont_splash_screen()) {
mmss_clock_disable();
}
return 0;
}
int mdp_dsi_cmd_off()
{
if(!target_cont_splash_screen())
{
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
writel(0xFF777713, MDP_INTR_CLEAR);
}
writel(0x00000000, MDP_INTR_EN);
return NO_ERROR;
}
int mdp_dsi_video_off()
{
if(!target_cont_splash_screen())
{
writel(0x00000000, MDP_DSI_VIDEO_EN);
mdelay(60);
writel(0x00000000, MDP_INTR_ENABLE);
writel(0x00000003, MDP_OVERLAYPROC0_CFG);
}
return NO_ERROR;
}
int mdp_dsi_cmd_off(void)
{
if (!target_cont_splash_screen()) {
mdp_dma_off();
/*
* Allow sometime for the DMA channel to
* stop the data transfer
*/
mdelay(10);
}
writel(0x00000000, MDP_INTR_ENABLE);
writel(0x01ffffff, MDP_INTR_CLEAR);
return NO_ERROR;
}
int mipi_dsi_off(struct msm_panel_info *pinfo)
{
if(!target_cont_splash_screen())
{
mdss_dsi_panel_shutdown(pinfo);
writel(0, pinfo->mipi.ctl_base + CLK_CTRL);
writel(0x1F1, pinfo->mipi.ctl_base + CTRL);
}
writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL);
if (pinfo->mipi.broadcast)
writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL);
return NO_ERROR;
}
static int msm8974_mdss_edp_panel_clock(int enable)
{
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
edp_clk_enable();
} else if (!target_cont_splash_screen()) {
/* Add here for continuous splash */
edp_clk_disable();
mdp_clock_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
int mdp_dsi_cmd_off()
{
if(!target_cont_splash_screen())
{
mdp_dma_off();
/*
* Allow sometime for the DMA channel to
* stop the data transfer
*/
mdelay(10);
writel(0x00000000, MDP_INTR_ENABLE);
writel(0x00000003, MDP_OVERLAYPROC0_CFG);
}
return NO_ERROR;
}
int mdp_dsi_video_off()
{
if(!target_cont_splash_screen())
{
writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
writel(0xFF777713, MDP_INTR_CLEAR);
}
writel(0x00000000, MDP_INTR_EN);
return NO_ERROR;
}
static int fusion3_mtp_panel_power(int enable)
{
unsigned int lcd_id_det = 2;
if (enable) {
/* Set and enabale LDO2 1.2V for VDDA_MIPI_DSI0/1_PLL */
pm8921_ldo_set_voltage(LDO_2, LDO_VOLTAGE_1_2V);
mi_display_gpio_init();
/* Initial condition */
pmic8921_gpio_set(PM8921_GPIO_PANEL_RESET, 0);
pmic8921_gpio_set(PM8921_GPIO_LCD_DCDC_EN, 0);
pm8921_ldo_clear_voltage(LDO_23);
mdelay(8);
/* Enable LVS7 */
pm8921_low_voltage_switch_enable(lvs_7);
pm8921_ldo_set_voltage(LDO_23, LDO_VOLTAGE_1_8V);
mdelay(10);
/* Enable VSP VSN */
pmic8921_gpio_set(PM8921_GPIO_LCD_DCDC_EN, 1);
mdelay(8);
/* Reset */
pmic8921_gpio_set(PM8921_GPIO_PANEL_RESET, 1);
mdelay(3);
lcd_id_det = pmic8921_gpio_get(PM8921_GPIO_PANEL_ID);
} else {
if (!target_cont_splash_screen()) {
/* Reset down */
pmic8921_gpio_set(PM8921_GPIO_PANEL_RESET, 0);
/* Disable VSP VSN */
pmic8921_gpio_set(PM8921_GPIO_LCD_DCDC_EN, 0);
mdelay(8);
/* Disable 1V8 */
pm8921_ldo_clear_voltage(LDO_23);
}
}
return 0;
}
int mipi_hx8389b_panel_dsi_config(int on)
{
if (on) {
gpio_config(78, 0x1);
gpio_set(78, 0x1);
mdelay(20);
gpio_set(78, 0x0);
mdelay(20);
gpio_set(78, 0x1);
mdelay(20);
} else {
if (!target_cont_splash_screen()) {
gpio_set(78, 0x0);
pcom_set_backlight(0);
}
}
return 0;
}
int mipi_dsi_off()
{
if(!target_cont_splash_screen())
{
writel(0, DSI_CLK_CTRL);
writel(0x1F1, DSI_CTRL);
writel(0x00000001, DSIPHY_SW_RESET);
writel(0x00000000, DSIPHY_SW_RESET);
mdelay(10);
writel(0x0001, DSI_SOFT_RESET);
writel(0x0000, DSI_SOFT_RESET);
writel(0x1115501, DSI_INT_CTRL);
writel(0, DSI_CTRL);
}
writel(0x1115501, DSI_INT_CTRL);
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
int32_t ret = 0;
struct mdss_dsi_pll_config *pll_data;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
pll_data->vco_delay = VCO_DELAY_USEC;
if (enable) {
mdp_gdsc_ctrl(enable);
mdss_bus_clocks_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mdss_bus_clocks_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE);
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE))
dprintf(CRITICAL, "Not able to enable the pll\n");
gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi);
mdp_clock_disable();
mdss_bus_clocks_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
int mdp_dsi_video_off(struct msm_panel_info *pinfo)
{
uint32_t timing_engine_en;
if (pinfo->dest == DISPLAY_1)
timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
else
timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
if(!target_cont_splash_screen())
{
writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
writel(0xFF777713, MDP_INTR_CLEAR);
}
writel(0x00000000, MDP_INTR_EN);
return NO_ERROR;
}
void mipi_dsi_shutdown(void)
{
#if (DISPLAY_TYPE_MDSS == 0)
if(!target_cont_splash_screen())
{
mdp_shutdown();
writel(0x01010101, DSI_INT_CTRL);
writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
writel(0, DSI_CLK_CTRL);
writel(0, DSI_CTRL);
writel(0, DSIPHY_PLL_CTRL(0));
}
else
{
/* To keep the splash screen displayed till kernel driver takes
control, do not turn off the video mode engine and clocks.
Only disabling the MIPI DSI IRQs */
writel(0x01010101, DSI_INT_CTRL);
writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
}
#endif
}
int mipi_nt35510_panel_dsi_config(int on)
{
if (on) {
gpio_config(96, GPIO_OUTPUT);
/*
* As per the specification follow the sequence to put lcd
* backlight in one wire mode.
*/
gpio_set(96, 0x1);
udelay(190);
gpio_set(96, 0x0);
udelay(286);
gpio_set(96, 0x1);
udelay(50);
gpio_config(35, GPIO_OUTPUT);
gpio_set(35, 0x1);
gpio_config(40, GPIO_OUTPUT);
gpio_set(40, 0x1);
gpio_config(85, GPIO_OUTPUT);
gpio_set(85, 0x1);
mdelay(20);
gpio_set(85, 0x0);
mdelay(20);
gpio_set(85, 0x1);
mdelay(20);
} else {
if (!target_cont_splash_screen()) {
gpio_set(96, 0x0);
gpio_set(35, 0x0);
gpio_set(40, 0x0);
}
}
return 0;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
int32_t ret;
struct mdss_dsi_pll_config *pll_data;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clocks_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
mmss_dsi_clocks_disable();
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
static int msm8974_backlight_on()
{
static struct pm8x41_wled_data wled_ctrl = {
.mod_scheme = 0xC3,
.led1_brightness = (0x0F << 8) | 0xEF,
.led2_brightness = (0x0F << 8) | 0xEF,
.led3_brightness = (0x0F << 8) | 0xEF,
.max_duty_cycle = 0x01,
};
pm8x41_wled_config(&wled_ctrl);
pm8x41_wled_sink_control(1);
pm8x41_wled_iled_sync_control(1);
pm8x41_wled_enable(1);
return 0;
}
static int msm8974_mdss_dsi_panel_clock(uint8_t enable)
{
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_uniphy_pll_config();
mmss_clock_init();
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable();
mdp_clock_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
/* Pull DISP_RST_N high to get panel out of reset */
static void msm8974_mdss_mipi_panel_reset(uint8_t enable)
{
struct pm8x41_gpio gpio19_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = PM_GPIO_OUT_DRIVE_MED,
};
pm8x41_gpio_config(19, &gpio19_param);
if (enable) {
gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
mdelay(2);
pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
mdelay(5);
pm8x41_gpio_set(19, PM_GPIO_FUNC_HIGH);
mdelay(2);
gpio_set(58, 2);
} else {
gpio19_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
pm8x41_gpio_config(19, &gpio19_param);
pm8x41_gpio_set(19, PM_GPIO_FUNC_LOW);
gpio_set(58, 2);
}
}
static int msm8974_mipi_panel_power(uint8_t enable)
{
if (enable) {
/* Enable backlight */
msm8974_backlight_on();
/* Turn on LDO8 for lcd1 mipi vdd */
dprintf(SPEW, " Setting LDO22\n");
pm8x41_ldo_set_voltage("LDO22", 3000000);
pm8x41_ldo_control("LDO22", enable);
dprintf(SPEW, " Setting LDO12\n");
/* Turn on LDO23 for lcd1 mipi vddio */
pm8x41_ldo_set_voltage("LDO12", 1800000);
pm8x41_ldo_control("LDO12", enable);
dprintf(SPEW, " Setting LDO2\n");
/* Turn on LDO2 for vdda_mipi_dsi */
pm8x41_ldo_set_voltage("LDO2", 1200000);
pm8x41_ldo_control("LDO2", enable);
dprintf(SPEW, " Panel Reset \n");
/* Panel Reset */
msm8974_mdss_mipi_panel_reset(enable);
dprintf(SPEW, " Panel Reset Done\n");
} else {
msm8974_mdss_mipi_panel_reset(enable);
pm8x41_wled_enable(enable);
pm8x41_ldo_control("LDO2", enable);
pm8x41_ldo_control("LDO22", enable);
}
return 0;
}
void display_init(void)
{
uint32_t hw_id = board_hardware_id();
uint32_t soc_ver = board_soc_version();
dprintf(INFO, "display_init(),target_id=%d.\n", hw_id);
switch (hw_id) {
case HW_PLATFORM_MTP:
case HW_PLATFORM_FLUID:
case HW_PLATFORM_SURF:
mipi_toshiba_video_720p_init(&(panel.panel_info));
panel.clk_func = msm8974_mdss_dsi_panel_clock;
panel.power_func = msm8974_mipi_panel_power;
panel.fb.base = MIPI_FB_ADDR;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
panel.fb.stride = panel.panel_info.xres;
panel.fb.bpp = panel.panel_info.bpp;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_50;
break;
default:
return;
};
if (msm_display_init(&panel)) {
dprintf(CRITICAL, "Display init failed!\n");
return;
}
display_enable = 1;
}
void mdp_disable(void)
{
if (!target_cont_splash_screen())
writel(0x00000000, MDP_DSI_VIDEO_EN);
}
void mdp_clock_disable(void)
{
if (!target_cont_splash_screen())
clock_disable(MDP_CLK);
clock_disable(MDP_P_CLK);
}
static void msm8960_backlight_on(void)
{
struct pm8921_gpio backlight_pwm = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = 0,
.output_value = 0,
.pull = PM_GPIO_PULL_NO,
.vin_sel = 2,
.out_strength = PM_GPIO_STRENGTH_HIGH,
.function = PM_GPIO_FUNC_1,
.inv_int_pol = 0,
};
int rc = pm8921_gpio_config(PM_GPIO(24), &backlight_pwm);
if (rc)
dprintf(CRITICAL, "FAIL pm8921_gpio_config(): rc=%d.\n", rc);
}
/* Pull DISP_RST_N high to get panel out of reset */
static void msm8960_mipi_panel_reset(void)
{
struct pm8921_gpio gpio43_param = {
.direction = PM_GPIO_DIR_OUT,
.output_buffer = 0,
.output_value = 1,
.pull = PM_GPIO_PULL_UP_30,
.vin_sel = 2,
.out_strength = PM_GPIO_STRENGTH_HIGH,
.function = PM_GPIO_FUNC_PAIRED,
.inv_int_pol = 0,
.disable_pin = 0,
};
pm8921_gpio_config(PM_GPIO(43), &gpio43_param);
}
static int msm8960_mipi_panel_clock(int enable)
{
if (enable) {
mdp_clock_init();
mmss_clock_init();
} else if(!target_cont_splash_screen()) {
mmss_clock_disable();
}
return 0;
}
static int msm8960_mipi_panel_power(int enable)
{
if (enable) {
msm8960_backlight_on();
/* Turn on LDO8 for lcd1 mipi vdd */
pm8921_ldo_set_voltage(LDO_8, LDO_VOLTAGE_3_0V);
/* Turn on LDO23 for lcd1 mipi vddio */
pm8921_ldo_set_voltage(LDO_23, LDO_VOLTAGE_1_8V);
/* Turn on LDO2 for vdda_mipi_dsi */
pm8921_ldo_set_voltage(LDO_2, LDO_VOLTAGE_1_2V);
msm8960_mipi_panel_reset();
}
return 0;
}
void display_init(void)
{
dprintf(CRITICAL, "display_init\n");
switch (board_target_id()) {
case LINUX_MACHTYPE_8064_CDP:
lvds_chimei_wxga_init(&(panel.panel_info));
panel.clk_func = apq8064_lvds_clock;
panel.power_func = apq8064_lvds_panel_power;
panel.fb.base = 0x80B00000;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
panel.fb.stride = panel.panel_info.xres;
panel.fb.bpp = panel.panel_info.bpp;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_44;
break;
case LINUX_MACHTYPE_8064_MTP:
mipi_toshiba_video_wsvga_init(&(panel.panel_info));
panel.clk_func = fusion3_mtp_clock;
panel.power_func = fusion3_mtp_panel_power;
panel.fb.base = 0x89000000;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
panel.fb.stride = panel.panel_info.xres;
panel.fb.bpp = panel.panel_info.bpp;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_44;
break;
case LINUX_MACHTYPE_8960_CDP:
case LINUX_MACHTYPE_8960_MTP:
case LINUX_MACHTYPE_8960_FLUID:
case LINUX_MACHTYPE_8960_LIQUID:
mipi_toshiba_video_wsvga_init(&(panel.panel_info));
panel.clk_func = msm8960_mipi_panel_clock;
panel.power_func = msm8960_mipi_panel_power;
panel.fb.base = 0x89000000;
panel.fb.width = panel.panel_info.xres;
panel.fb.height = panel.panel_info.yres;
panel.fb.stride = panel.panel_info.xres;
panel.fb.bpp = panel.panel_info.bpp;
panel.fb.format = FB_FORMAT_RGB888;
panel.mdp_rev = MDP_REV_42;
break;
default:
return;
};
if (msm_display_init(&panel)) {
dprintf(CRITICAL, "Display init failed!\n");
return;
}
display_image_on_screen();
display_enable = 1;
}
void display_shutdown(void)
{
if (display_enable)
msm_display_off();
}
int mdp_lcdc_off(void)
{
if(!target_cont_splash_screen())
writel(0x0, MDP_LCDC_EN);
return NO_ERROR;
}
bool gcdb_display_cmdline_arg(char *panel_name, char *pbuf, uint16_t buf_size)
{
char *dsi_id = NULL;
char *panel_node = NULL;
char *slave_panel_node = NULL;
uint16_t dsi_id_len = 0, panel_node_len = 0, slave_panel_node_len = 0;
uint32_t arg_size = 0;
bool ret = true;
bool rc;
char *default_str;
int panel_mode = SPLIT_DISPLAY_FLAG | DUAL_PIPE_FLAG | DST_SPLIT_FLAG;
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
char *sctl_string;
panel_name += strspn(panel_name, " ");
rc = mdss_dsi_set_panel_node(panel_name, &dsi_id, &panel_node,
&slave_panel_node, &panel_mode);
if (!rc) {
if (panelstruct.paneldata && target_cont_splash_screen()) {
dsi_id = panelstruct.paneldata->panel_controller;
panel_node = panelstruct.paneldata->panel_node_id;
panel_mode =
panelstruct.paneldata->panel_operating_mode &
panel_mode;
slave_panel_node =
panelstruct.paneldata->slave_panel_node_id;
} else {
if (target_is_edp())
default_str = "0:edp:";
else
default_str = "0:dsi:0:";
arg_size = prefix_string_len + strlen(default_str);
if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
return false;
}
strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
pbuf += prefix_string_len;
buf_size -= prefix_string_len;
strlcpy(pbuf, default_str, buf_size);
return true;
}
}
if (dsi_id == NULL || panel_node == NULL) {
dprintf(CRITICAL, "panel node or dsi ctrl not present\n");
return false;
}
if (((panel_mode & SPLIT_DISPLAY_FLAG) ||
(panel_mode & DST_SPLIT_FLAG)) && slave_panel_node == NULL) {
dprintf(CRITICAL, "slave node not present in dual dsi case\n");
return false;
}
dsi_id_len = strlen(dsi_id);
panel_node_len = strlen(panel_node);
if (!slave_panel_node || !strcmp(slave_panel_node, ""))
slave_panel_node = NO_PANEL_CONFIG;
slave_panel_node_len = strlen(slave_panel_node);
arg_size = prefix_string_len + dsi_id_len + panel_node_len +
LK_OVERRIDE_PANEL_LEN + 1;
if (panelstruct.paneldata &&
!strcmp(panelstruct.paneldata->panel_destination, "DISPLAY_2"))
sctl_string = DSI_0_STRING;
else
sctl_string = DSI_1_STRING;
arg_size += strlen(sctl_string) + slave_panel_node_len;
if (buf_size < arg_size) {
dprintf(CRITICAL, "display command line buffer is small\n");
ret = false;
} else {
strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
pbuf += prefix_string_len;
buf_size -= prefix_string_len;
strlcpy(pbuf, LK_OVERRIDE_PANEL, buf_size);
pbuf += LK_OVERRIDE_PANEL_LEN;
buf_size -= LK_OVERRIDE_PANEL_LEN;
strlcpy(pbuf, dsi_id, buf_size);
pbuf += dsi_id_len;
buf_size -= dsi_id_len;
strlcpy(pbuf, panel_node, buf_size);
pbuf += panel_node_len;
buf_size -= panel_node_len;
strlcpy(pbuf, sctl_string, buf_size);
pbuf += strlen(sctl_string);
buf_size -= strlen(sctl_string);
strlcpy(pbuf, slave_panel_node, buf_size);
}
return ret;
}
int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.function = PM_GPIO_FUNC_1,
.vin_sel = 2, /* VIN_2 */
.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
if (enable) {
pm8x41_gpio_config(7, &pwmgpio_param);
/* lpg channel 2 */
pm8x41_lpg_write(3, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(3, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(3, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
pm8x41_lpg_write(3, 0x44, 0xcc); /* LPG_VALUE_LSB */
pm8x41_lpg_write(3, 0x45, 0x00); /* LPG_VALUE_MSB */
pm8x41_lpg_write(3, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
pm8x41_lpg_write(3, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi &&
!(pinfo->mipi.broadcast)) {
mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI1_BASE);
}
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
mmss_dsi_clock_disable(dual_dsi);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
uint32_t i = 0;
if (enable) {
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength, enable_gpio.pin_state);
gpio_tlmm_config(bkl_gpio.pin_id, 0,
bkl_gpio.pin_direction, bkl_gpio.pin_pull,
bkl_gpio.pin_strength, bkl_gpio.pin_state);
gpio_set(enable_gpio.pin_id, 2);
gpio_set(bkl_gpio.pin_id, 2);
/* reset */
for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
if (resetseq->pin_state[i] == GPIO_STATE_LOW)
gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
else
gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
mdelay(resetseq->sleep[i]);
}
} else {
gpio_set(reset_gpio.pin_id, 0);
gpio_set(enable_gpio.pin_id, 0);
gpio_set(bkl_gpio.pin_id, 0);
}
return NO_ERROR;
}
