Example #1
0
void target_usb_stop(void)
{

	/* Disable VBUS mimicing in the controller. */
	if (target_needs_vbus_mimic())
		ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
}
void target_usb_stop(void)
{
	uint32_t platform = board_platform_id();

	/* Disable VBUS mimicing in the controller. */
	if (target_needs_vbus_mimic())
		ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
}
Example #3
0
/* Do target specific usb initialization */
void target_usb_init(void)
{
	uint32_t val;

	/* Enable secondary USB PHY on DragonBoard8074 */
	if (board_hardware_id() == HW_PLATFORM_DRAGON) {
		/* Route ChipIDea to use secondary USB HS port2 */
		writel_relaxed(1, USB2_PHY_SEL);

		/* Enable access to secondary PHY by clamping the low
		* voltage interface between DVDD of the PHY and Vddcx
		* (set bit16 (USB2_PHY_HS2_DIG_CLAMP_N_2) = 1) */
		writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_SEC_CTRL)
				| 0x00010000, USB_OTG_HS_PHY_SEC_CTRL);

		/* Perform power-on-reset of the PHY.
		*  Delay values are arbitrary */
		writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL)|1,
				USB_OTG_HS_PHY_CTRL);
		thread_sleep(10);
		writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL) & 0xFFFFFFFE,
				USB_OTG_HS_PHY_CTRL);
		thread_sleep(10);

		/* Enable HSUSB PHY port for ULPI interface,
		* then configure related parameters within the PHY */
		writel_relaxed(((readl_relaxed(USB_PORTSC) & 0xC0000000)
				| 0x8c000004), USB_PORTSC);
	}

	if (target_needs_vbus_mimic())
	{
		/* Select and enable external configuration with USB PHY */
		ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);

		/* Enable sess_vld */
		val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
		writel(val, USB_GENCONFIG_2);

		/* Enable external vbus configuration in the LINK */
		val = readl(USB_USBCMD);
		val |= SESS_VLD_CTRL;
		writel(val, USB_USBCMD);
	}
}
Example #4
0
/* Do target specific usb initialization */
void target_usb_init(void)
{
	uint32_t val;

	if (target_needs_vbus_mimic()) {
		/* Select and enable external configuration with USB PHY */
		ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);

		/* Enable sess_vld */
		val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
		writel(val, USB_GENCONFIG_2);

		/* Enable external vbus configuration in the LINK */
		val = readl(USB_USBCMD);
		val |= SESS_VLD_CTRL;
		writel(val, USB_USBCMD);
	}
}