void kinetis_mdm_probe(ADIv5_AP_t *ap) { switch(ap->idr) { case KINETIS_MDM_IDR_KZ03: case KINETIS_MDM_IDR_K22F: break; default: return; } target *t = target_new(); adiv5_ap_ref(ap); t->priv = ap; t->priv_free = (void*)adiv5_ap_unref; t->driver = "Kinetis Recovery (MDM-AP)"; t->attach = (void*)nop_function; t->detach = (void*)nop_function; t->check_error = (void*)nop_function; t->mem_read = (void*)nop_function; t->mem_write = (void*)nop_function; t->regs_size = 4; t->regs_read = (void*)nop_function; t->regs_write = (void*)nop_function; t->reset = (void*)nop_function; t->halt_request = (void*)nop_function; t->halt_poll = mdm_halt_poll; t->halt_resume = (void*)nop_function; target_add_commands(t, kinetis_mdm_cmd_list, t->driver); }
bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base) { target *t; t = target_new(); adiv5_ap_ref(apb); struct cortexa_priv *priv = calloc(1, sizeof(*priv)); t->priv = priv; t->priv_free = free; priv->apb = apb; /* FIXME Find a better way to find the AHB. This is likely to be * device specific. */ priv->ahb = adiv5_new_ap(apb->dp, 0); adiv5_ap_ref(priv->ahb); if ((priv->ahb->idr & 0xfffe00f) == 0x4770001) { /* This is an AHB */ t->mem_read = cortexa_mem_read; t->mem_write = cortexa_mem_write; } else { /* This is not an AHB, fall back to slow APB access */ adiv5_ap_unref(priv->ahb); priv->ahb = NULL; t->mem_read = cortexa_slow_mem_read; t->mem_write = cortexa_slow_mem_write; } priv->base = debug_base; /* Set up APB CSW, we won't touch this again */ uint32_t csw = apb->csw | ADIV5_AP_CSW_SIZE_WORD; adiv5_ap_write(apb, ADIV5_AP_CSW, csw); uint32_t dbgdidr = apb_read(t, DBGDIDR); priv->hw_breakpoint_max = ((dbgdidr >> 24) & 15)+1; t->check_error = cortexa_check_error; t->driver = cortexa_driver_str; t->attach = cortexa_attach; t->detach = cortexa_detach; t->tdesc = tdesc_cortex_a; t->regs_read = cortexa_regs_read; t->regs_write = cortexa_regs_write; t->reset = cortexa_reset; t->halt_request = cortexa_halt_request; t->halt_poll = cortexa_halt_poll; t->halt_resume = cortexa_halt_resume; t->regs_size = sizeof(priv->reg_cache); t->breakwatch_set = cortexa_breakwatch_set; t->breakwatch_clear = cortexa_breakwatch_clear; return true; }