/*************************************************************************//**
*****************************************************************************/
void HAL_TimerInit(void)
{
halTimerIrqCount = 0;
// System Tick
sysclk_enable_peripheral_clock(SYSTIMER_TICK_CHANNEL_ID);
tc_init(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC);
NVIC_DisableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
NVIC_ClearPendingIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
NVIC_EnableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
tc_enable_interrupt(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_IER_CPCS);
tc_write_rc(SYSTIMER, SYSTIMER_TICK_CHANNEL, TIMER_TOP);
tc_start(SYSTIMER, SYSTIMER_TICK_CHANNEL);
sysclk_enable_peripheral_clock(SYSTIMER_DELAY_CHANNEL_ID);
tc_init(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_CPCDIS | TC_CMR_CPCSTOP);
NVIC_DisableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
NVIC_ClearPendingIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
NVIC_EnableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
tc_enable_interrupt(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_IER_CPCS);
}
static void
dec_maxine_tc_init(void)
{
#if defined(MIPS3)
static struct timecounter tc3 = {
.tc_get_timecount = (timecounter_get_t *)mips3_cp0_count_read,
.tc_counter_mask = ~0u,
.tc_name = "mips3_cp0_counter",
.tc_quality = 200,
};
#endif
static struct timecounter tc = {
.tc_get_timecount = dec_maxine_get_timecount,
.tc_quality = 100,
.tc_frequency = 1000000,
.tc_counter_mask = ~0,
.tc_name = "maxine_fctr",
};
tc_init(&tc);
#if defined(MIPS3)
if (MIPS_HAS_CLOCK) {
tc3.tc_frequency = mips_options.mips_cpu_mhz * 1000000;
tc_init(&tc3);
}
#endif
}
/* 81 */
int calc_init_81(LPCALC lpCalc, char *version) {
/* INTIALIZE 81 */
//v2 is basically an 82
if (version[0] == '2') {
memory_init_81(&lpCalc->mem_c);
tc_init(&lpCalc->timer_c, MHZ_2);
CPU_init(&lpCalc->cpu, &lpCalc->mem_c, &lpCalc->timer_c);
ClearDevices(&lpCalc->cpu);
device_init_83(&lpCalc->cpu, 1);
} else {
memory_init_81(&lpCalc->mem_c);
tc_init(&lpCalc->timer_c, MHZ_2);
CPU_init(&lpCalc->cpu, &lpCalc->mem_c, &lpCalc->timer_c);
ClearDevices(&lpCalc->cpu);
device_init_81(&lpCalc->cpu);
}
/* END INTIALIZE 81 */
#ifdef WINVER // FIXME: dirty cheater!
lpCalc->flash_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.flash_size, sizeof(LPBREAKPOINT *));
lpCalc->ram_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.ram_size, sizeof(LPBREAKPOINT *));
if (version[0] == '2') {
lpCalc->audio = &lpCalc->cpu.pio.link->audio;
lpCalc->audio->enabled = FALSE;
lpCalc->audio->init = FALSE;
lpCalc->audio->timer_c = &lpCalc->timer_c;
}
#endif
return TRUE;
}
void sam_timer_early_init(void)
{
#if 0
pmc_enable_periph_clk(ID_TC0);
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = MCLK; // sysclk_get_cpu_hz();
tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, 0xffff); // slowest we can run
/* Configure and enable interrupt on RC compare */
NVIC_SetPriority(ID_TC0, arm_cm_highest_priority());
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#endif
tc_start(TC0, 0);
arm_cm_systick_init(MCLK);
}
void *platform_configure_timer(platform_hw_timer_callback_t bus_tc_cb_ptr)
{
struct tc_config timer_config;
system_interrupt_enter_critical_section();
if (hw_timers[0].timer_usage == 0)
{
hw_timers[0].timer_usage = 1;
platform_cc1_cb = bus_tc_cb_ptr;
tc_get_config_defaults(&timer_config);
timer_config.clock_prescaler = TC_CLOCK_PRESCALER_DIV1;
timer_config.oneshot = true;
timer_config.counter_size = TC_COUNTER_SIZE_32BIT;
timer_config.count_direction = TC_COUNT_DIRECTION_UP;
tc_init(&bus_tc_instance, CONF_BUS_TC_MODULE, &timer_config);
timer_count_per_ms = ((system_gclk_gen_get_hz(timer_config.clock_source)) /1000);
tc_set_count_value(&bus_tc_instance, 0);
tc_enable(&bus_tc_instance);
tc_stop_counter(&bus_tc_instance);
tc_register_callback(&bus_tc_instance, tc_cc1_cb,
TC_CALLBACK_OVERFLOW);
tc_enable_callback(&bus_tc_instance, TC_CALLBACK_OVERFLOW);
hw_timers[0].timer_frequency = (system_gclk_gen_get_hz(timer_config.clock_source));
hw_timers[0].timer_instance = bus_tc_instance;
system_interrupt_leave_critical_section();
return (&hw_timers[0]);
}
system_interrupt_leave_critical_section();
return NULL;
}
static void configure_tc(struct tc_module *tc_instance)
{
//! [setup_6]
struct tc_config config_tc;
struct tc_events config_events;
//! [setup_6]
//! [setup_7]
tc_get_config_defaults(&config_tc);
//! [setup_7]
//! [setup_8]
config_tc.counter_size = TC_COUNTER_SIZE_8BIT;
config_tc.wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ;
config_tc.clock_source = GCLK_GENERATOR_1;
config_tc.clock_prescaler = TC_CLOCK_PRESCALER_DIV64;
//! [setup_8]
//! [setup_9]
tc_init(tc_instance, CONF_TC_MODULE, &config_tc);
//! [setup_9]
//! [setup_10]
config_events.generate_event_on_overflow = true;
tc_enable_events(tc_instance, &config_events);
//! [setup_10]
//! [setup_11]
tc_enable(tc_instance);
//! [setup_11]
}
void
acpitimerattach(struct device *parent, struct device *self, void *aux)
{
struct acpitimer_softc *sc = (struct acpitimer_softc *) self;
struct acpi_softc *psc = (struct acpi_softc *) parent;
int rc;
if (psc->sc_fadt->hdr_revision >= 3 &&
psc->sc_fadt->x_pm_tmr_blk.address != 0)
rc = acpi_map_address(psc, &psc->sc_fadt->x_pm_tmr_blk, 0,
psc->sc_fadt->pm_tmr_len, &sc->sc_ioh, &sc->sc_iot);
else
rc = acpi_map_address(psc, NULL, psc->sc_fadt->pm_tmr_blk,
psc->sc_fadt->pm_tmr_len, &sc->sc_ioh, &sc->sc_iot);
if (rc) {
printf(": can't map i/o space\n");
return;
}
printf(": %d Hz, %d bits\n", ACPI_FREQUENCY,
psc->sc_fadt->flags & FADT_TMR_VAL_EXT ? 32 : 24);
if (psc->sc_fadt->flags & FADT_TMR_VAL_EXT)
acpi_timecounter.tc_counter_mask = 0xffffffffU;
acpi_timecounter.tc_priv = sc;
acpi_timecounter.tc_name = sc->sc_dev.dv_xname;
tc_init(&acpi_timecounter);
}
/*---------------------------------------------------------------------------*/
void
clock_init(void)
{
#define TIMER_PERIOD UINT16_MAX
#define TIMER TC3
struct tc_config cfg;
tc_get_config_defaults(&cfg);
cfg.clock_source = GCLK_GENERATOR_5;
cfg.clock_prescaler = TC_CLOCK_PRESCALER_DIV1;
cfg.run_in_standby = false;
cfg.counter_16_bit.compare_capture_channel[0] = TIMER_PERIOD;
tc_init(&tc_instance, TIMER, &cfg);
/* tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_OVERFLOW);*/
tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_CC_CHANNEL0);
/* tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_CC_CHANNEL1);
tc_register_callback(&tc_instance, clock_irq_callback, TC_CALLBACK_ERROR);*/
/* tc_enable_callback(&tc_instance, TC_CALLBACK_OVERFLOW);*/
tc_enable_callback(&tc_instance, TC_CALLBACK_CC_CHANNEL0);
/* tc_enable_callback(&tc_instance, TC_CALLBACK_CC_CHANNEL1);
tc_enable_callback(&tc_instance, TC_CALLBACK_ERROR);*/
tc_enable(&tc_instance);
}
void
cpu_initclocks(void)
{
static struct timecounter tc = {
.tc_get_timecount = get_itimer_count,
.tc_name = "itimer",
.tc_counter_mask = ~0,
.tc_quality = 100,
};
extern u_int cpu_hzticks;
u_int time_inval;
tc.tc_frequency = cpu_hzticks * hz;
/* Start the interval timer. */
mfctl(CR_ITMR, time_inval);
mtctl(time_inval + cpu_hzticks, CR_ITMR);
tc_init(&tc);
}
unsigned
get_itimer_count(struct timecounter *tc)
{
uint32_t val;
mfctl(CR_ITMR, val);
return val;
}
/*
* This is called from the psycho and sbus drivers. It does not directly
* attach to the nexus because it shares register space with the bridge in
* question.
*/
void
sparc64_counter_init(const char *name, bus_space_tag_t tag,
bus_space_handle_t handle, bus_addr_t offset)
{
struct timecounter *tc;
struct ct_softc *sc;
printf("initializing counter-timer\n");
/*
* Turn off interrupts from both counters. Set the limit to the
* maximum value (although that should not change anything with
* CTLR_INTEN and CTLR_PERIODIC off).
*/
bus_space_write_8(tag, handle, offset + CTR_CT0 + CTR_LIMIT,
COUNTER_MASK);
bus_space_write_8(tag, handle, offset + CTR_CT1 + CTR_LIMIT,
COUNTER_MASK);
/* Register as a time counter. */
tc = malloc(sizeof(*tc), M_DEVBUF, M_WAITOK | M_ZERO);
sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK);
sc->sc_tag = tag;
sc->sc_handle = handle;
sc->sc_offset = offset + CTR_CT0;
tc->tc_get_timecount = counter_get_timecount;
tc->tc_counter_mask = COUNTER_MASK;
tc->tc_frequency = COUNTER_FREQ;
tc->tc_name = strdup(name, M_DEVBUF);
tc->tc_priv = sc;
tc->tc_quality = COUNTER_QUALITY;
tc_init(tc);
}
static void
at91_st_initclocks(device_t dev, struct at91_st_softc *sc)
{
int rel_value;
/*
* Real time counter increments every clock cycle, need to set before
* initializing clocks so that DELAY works.
*/
WR4(ST_RTMR, 1);
/* disable watchdog timer */
WR4(ST_WDMR, 0);
rel_value = 32768 / hz;
if (rel_value < 1)
rel_value = 1;
if (32768 % hz) {
device_printf(dev, "Cannot get %d Hz clock; using %dHz\n", hz,
32768 / rel_value);
hz = 32768 / rel_value;
tick = 1000000 / hz;
}
WR4(ST_PIMR, rel_value);
/* Enable PITS interrupts. */
WR4(ST_IER, ST_SR_PITS);
tc_init(&at91_st_timecounter);
}
void config_uart(void){
/* configura pinos */
gpio_configure_group(PINS_UART0_PIO, PINS_UART0, PINS_UART0_FLAGS);
/* ativa clock */
sysclk_enable_peripheral_clock(CONSOLE_UART_ID);
/* Configuração UART */
const usart_serial_options_t uart_serial_options = {
.baudrate = CONF_UART_BAUDRATE,
.paritytype = UART_MR_PAR_NO,
.stopbits = 0
};
stdio_serial_init((Usart *)CONF_UART, &uart_serial_options);
}
static void configure_tc(void)
{
uint32_t ul_sysclk = sysclk_get_cpu_hz();
pmc_enable_periph_clk(ID_TC0);
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
tc_write_rc(TC0, 0, 8192);
NVIC_EnableIRQ(ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
/**
* Configure Timer Counter 0 to generate an interrupt every 1s.
*/
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual está em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/*
* Ativa o clock do periférico TC 0
*/
pmc_enable_periph_clk(ID_TC0);
// Configura TC para operar no modo de comparação e trigger RC
tc_init(TC0,0,TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
// Valor para o contador de um em um segundo.
tc_write_rc(TC0,0,32768);
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0,0,TC_IER_CPCS);
tc_start(TC0, 0);
}
int main(void)
{
// Configure pin 7 on EXT1 as output
ioport_configure_pin(EXT1_PIN_7,IOPORT_DIR_OUTPUT);
sysclk_init();
board_init();
// Start TC and configure pin to get PWM output to LED on IO1 Xplained Pro extension board
tc_init();
while (1) {
struct pll_config pcfg;
/*
* Initial state: Running from RC32M prescalers with 16x
* prescaling of CLKsys, 2x prescaling for CLKper2 and 2x
* prescaling for CLKper.
*/
wait_for_btn_press();
/*
* Prescale CLKsys by 128x, prescale all peripheral clocks by 1.
*/
sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1);
wait_for_btn_press();
/*
* Switch to RC2M with 4x prescaling of CLKsys, 4x prescaling
* for CLKper2 and 1x prescaling for CLKper.
*/
osc_enable(OSC_ID_RC2MHZ);
do {} while (!osc_is_ready(OSC_ID_RC2MHZ));
sysclk_set_source(SYSCLK_SRC_RC2MHZ);
sysclk_set_prescalers(SYSCLK_PSADIV_4, SYSCLK_PSBCDIV_4_1);
osc_disable(OSC_ID_RC32MHZ);
wait_for_btn_press();
/*
* Switch to PLL with RC2M as reference and 4x multiplier.
* Prescale CLKsys by 128x, and all peripheral clocks by 1x.
*/
pll_config_init(&pcfg, PLL_SRC_RC2MHZ, 1, 4);
pll_enable(&pcfg, 0);
do {} while (!pll_is_locked(0));
sysclk_set_prescalers(SYSCLK_PSADIV_128, SYSCLK_PSBCDIV_1_1);
sysclk_set_source(SYSCLK_SRC_PLL);
wait_for_btn_press();
/*
* Go back to the initial state and start over.
*/
osc_enable(OSC_ID_RC32MHZ);
do {} while(!osc_is_ready(OSC_ID_RC32MHZ));
sysclk_set_source(SYSCLK_SRC_RC32MHZ);
sysclk_set_prescalers(SYSCLK_PSADIV_16, SYSCLK_PSBCDIV_2_2);
pll_disable(0);
osc_disable(OSC_ID_RC2MHZ);
}
}
/* 82 83 */
static BOOL calc_init_83(LPCALC lpCalc, char *os) {
/* INTIALIZE 83 */
memory_init_83(&lpCalc->mem_c);
tc_init(&lpCalc->timer_c, MHZ_6);
CPU_init(&lpCalc->cpu, &lpCalc->mem_c, &lpCalc->timer_c);
ClearDevices(&lpCalc->cpu);
if (lpCalc->model == TI_82) {
if (memcmp(os, "19.006", 6)==0) {
device_init_83(&lpCalc->cpu, 0);
} else {
device_init_83(&lpCalc->cpu, 1);
}
} else {
device_init_83(&lpCalc->cpu, 0);
}
/* END INTIALIZE 83 */
#ifdef WINVER // FIXME: dirty cheater!
lpCalc->flash_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.flash_size, sizeof(LPBREAKPOINT *));
lpCalc->ram_cond_break = (LPBREAKPOINT *) calloc(lpCalc->mem_c.ram_size, sizeof(LPBREAKPOINT *));
lpCalc->audio = &lpCalc->cpu.pio.link->audio;
lpCalc->audio->enabled = FALSE;
lpCalc->audio->init = FALSE;
lpCalc->audio->timer_c = &lpCalc->timer_c;
#endif
return TRUE;
}
//! [setup]
void configure_tc(void)
{
//! [setup_config]
struct tc_config config_tc;
//! [setup_config]
//! [setup_config_defaults]
tc_get_config_defaults(&config_tc);
//! [setup_config_defaults]
//! [setup_change_config]
config_tc.counter_size = TC_COUNTER_SIZE_16BIT;
config_tc.wave_generation = TC_WAVE_GENERATION_NORMAL_PWM;
config_tc.counter_16_bit.compare_capture_channel[0] = (0xFFFF / 4);
//! [setup_change_config]
//! [setup_change_config_pwm]
config_tc.pwm_channel[0].enabled = true;
config_tc.pwm_channel[0].pin_out = PWM_OUT_PIN;
config_tc.pwm_channel[0].pin_mux = PWM_OUT_MUX;
//! [setup_change_config_pwm]
//! [setup_set_config]
tc_init(&tc_instance, PWM_MODULE, &config_tc);
//! [setup_set_config]
//! [setup_enable]
tc_enable(&tc_instance);
//! [setup_enable]
}
void delay_init(void) /* Initializes the timer used for delays */
{
pmc_enable_periph_clk(ID_TC4);
tc_init(TC1,1,0); /* TC1, channel 1, TCLK1 och capturemode */
tc_set_block_mode(TC1,0);
tc_stop(TC1,1); /* making sure the timer does not run */
}
/**
* \internal
* \brief Test of tc_init() and tc_get_config_defaults()
*
* This test is used to initialize the tcx_module structs and associate the given
* hw module with the struct. This test should be run at the very beginning of
* testing as other tests depend on the result of this test.
*/
static void run_init_test(const struct test_case *test)
{
tc_get_config_defaults(&tc_test0_config);
enum status_code test1 = tc_init(&tc_test0_module, CONF_TEST_TC0, &tc_test0_config);
tc_get_config_defaults(&tc_test1_config);
enum status_code test2 = tc_init(&tc_test1_module, CONF_TEST_TC1, &tc_test1_config);
if ((test1 == STATUS_OK) && (test2 == STATUS_OK)) {
tc_init_success = true;
}
test_assert_true(test,
(test2 == STATUS_OK) && (test1 == STATUS_OK),
"Failed to initialize modules");
}
/**
* \brief Configure to trigger ADC by TIOA output of timer.
*/
static void configure_time_trigger(void)
{
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_TC0);
/* TIOA configuration */
gpio_configure_pin(PIN_TC0_TIOA0, PIN_TC0_TIOA0_FLAGS);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(1, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(TC0, 0, ul_tc_clks | TC_CMR_CPCTRG | TC_CMR_WAVE |
TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
TC0->TC_CHANNEL[0].TC_RA = (ul_sysclk / ul_div) / 2;
TC0->TC_CHANNEL[0].TC_RC = (ul_sysclk / ul_div) / 1;
/* Start the Timer. */
tc_start(TC0, 0);
/* Set TIOA0 trigger. */
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
adc_configure_trigger(ADC, ADC_TRIG_TIO_CH_0, 0);
#elif SAM3U
#ifdef ADC_12B
adc12b_configure_trigger(ADC12B, ADC12B_TRIG_TIO_CH_0);
#else
adc_configure_trigger(ADC, ADC_TRIG_TIO_CH_0);
#endif
#endif
}
//-------------------------------------------------------------------------------
// TCP client start
//-------------------------------------------------------------------------------
err_t ICACHE_FLASH_ATTR tc_go(void)
{
err_t err = ERR_USE;
if((tc_init_flg & TC_RUNNING) || iot_data_processing == NULL) return err; // выход, если процесс запущен или нечего запускать
#if DEBUGSOO > 4
os_printf("Run: %x, %u\n", iot_data_processing, iot_data_processing->min_interval);
#endif
err = tc_init(); // инициализация TCP
if(err == ERR_OK) {
tc_init_flg |= TC_RUNNING; // процесс запущен
run_error_timer(TCP_REQUEST_TIMEOUT); // обработать ошибки и продолжение
#if DEBUGSOO > 4
int i;
for (i = 0; i < DNS_TABLE_SIZE; ++i) {
os_printf("TDNS%d: %d, %s, " IPSTR " (%d)\n", i, dns_table[i].state, dns_table[i].name, IP2STR(&dns_table[i].ipaddr), dns_table[i].ttl);
}
#endif
err = dns_gethostbyname(iot_server_name, &tc_remote_ip, (dns_found_callback)tc_dns_found_callback, NULL);
#if DEBUGSOO > 4
os_printf("dns_gethostbyname(%s)=%d ", iot_server_name, err);
#endif
if(err == ERR_OK) { // Адрес разрешен из кэша или локальной таблицы
err = tcpsrv_client_start(tc_servcfg, tc_remote_ip.addr, DEFAULT_TC_HOST_PORT);
} else if(err == ERR_INPROGRESS) { // Запущен процесс разрешения имени с внешнего DNS
err = ERR_OK;
}
if (err != ERR_OK) {
tc_init_flg &= ~TC_RUNNING; // процесс не запущен
// tc_close();
}
}
return err;
}
void
cpu_initclocks(void)
{
int rel_value;
struct resource *irq;
int rid = 0;
void *ih;
device_t dev = timer_softc->sc_dev;
rel_value = 32768 / hz;
if (rel_value < 1)
rel_value = 1;
if (32768 % hz) {
printf("Cannot get %d Hz clock; using %dHz\n", hz, 32768 / rel_value);
hz = 32768 / rel_value;
tick = 1000000 / hz;
}
/* Disable all interrupts.�*/
WR4(ST_IDR, 0xffffffff);
/* The system timer shares the system irq (1) */
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1, 1, 1,
RF_ACTIVE | RF_SHAREABLE);
if (!irq)
panic("Unable to allocate irq for the system timer");
else
bus_setup_intr(dev, irq, INTR_TYPE_CLK,
clock_intr, NULL, NULL, &ih);
WR4(ST_PIMR, rel_value);
/* Enable PITS interrupts. */
WR4(ST_IER, ST_SR_PITS);
tc_init(&at91st_timecounter);
}
// Set the frequency of the generated tone. 0 means off.
void audioFrequencySet(uint32_t freq) {
// In order to avoid audio hiccups, don't do anything if setting
// same frequency.
if (currFreq == freq) {
return;
}
tc_stop(TC0, 0);
if (freq == 0) {
return;
}
// Find the best divisor for this frequency
uint32_t ul_div, ul_tcclks;
tc_find_mck_divisor(freq, SystemCoreClock,
&ul_div, &ul_tcclks, SystemCoreClock);
// Put Timer into wavesel up RC mode with TIOA at 50% duty cycle
// Clear TIOA at CPC match and set at CPA match
tc_init(TC0, 0, ul_tcclks | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_ACPC_CLEAR | TC_CMR_ACPA_SET);
uint16_t rcVal = (SystemCoreClock / ul_div) / freq;
tc_write_rc(TC0, 0, rcVal);
tc_write_ra(TC0, 0, rcVal / 2); // 50% duty cycle
// Start the thing
tc_start(TC0, 0);
currFreq = freq;
}
int main (void)
{
sysclk_init();
pmic_init();
port_init();
tc_init();
wdt_set_timeout_period(WDT_TIMEOUT_PERIOD_32CLK);
wdt_enable();
usart_init();
spi_init();
char str[200];
uint8_t count ;
count = sprintf(str,"RESET");
for (uint8_t i=0;i<count;i++)
usart_putchar(&USARTE0,str[i]);
nrf_init(Address);
sei();
for (uint8_t i=0;i<Max_Robot;i++)
{
Robot_D_tmp[2][i].RID=12;
}
while (1)
{
}
}
/*
* Initialize clock frequencies and start both clocks running.
*/
void
initclocks(void)
{
int i;
/*
* Set divisors to 1 (normal case) and let the machine-specific
* code do its bit.
*/
psdiv = 1;
/*
* provide minimum default time counter
* will only run at interrupt resolution
*/
intr_timecounter.tc_frequency = hz;
tc_init(&intr_timecounter);
cpu_initclocks();
/*
* Compute profhz and stathz, fix profhz if needed.
*/
i = stathz ? stathz : hz;
if (profhz == 0)
profhz = i;
psratio = profhz / i;
if (schedhz == 0) {
/* 16Hz is best */
hardscheddiv = hz / 16;
if (hardscheddiv <= 0)
panic("hardscheddiv");
}
}
void
platform_initclocks(void)
{
if (platform_timecounter != NULL)
tc_init(platform_timecounter);
}
/**
* \brief Initialize the timer counter (TC0).
*/
void sys_init_timing(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
/* Clear tick value. */
gs_ul_clk_tick = 0;
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC0);
/* Configure TC for a 1kHz frequency and trigger on RC compare. */
tc_find_mck_divisor(1000,
sysclk_get_main_hz(), &ul_div, &ul_tcclks,
sysclk_get_main_hz());
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (sysclk_get_main_hz() / ul_div) / 1000);
/* Configure and enable interrupt on RC compare. */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start timer. */
tc_start(TC0, 0);
}
void
cpu_initclocks(void)
{
if (clock_sc == NULL)
panic("Clock timer was not configured.");
if (stat_sc == NULL)
panic("Statistics timer was not configured.");
if (ref_sc == NULL)
panic("Microtime reference timer was not configured.");
/*
* We already have the timers running, but not generating interrupts.
* In addition, we've set stathz and profhz.
*/
printf("clock: hz=%d stathz=%d\n", hz, stathz);
/*
* The "cookie" parameter must be zero to pass the interrupt frame
* through to hardclock() and statclock().
*/
omap_intr_establish(clock_sc->sc_intr, IPL_CLOCK,
clock_sc->sc_dev.dv_xname, clockintr, 0);
omap_intr_establish(stat_sc->sc_intr, IPL_HIGH,
stat_sc->sc_dev.dv_xname, statintr, 0);
tc_init(&mpu_timecounter);
}
// [main_tc_configure]
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC */
pmc_enable_periph_clk(ID_TC0);
#if SAMG55
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_3);
pmc_switch_pck_to_sclk(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_3);
#endif
/** Configure TC for a 4Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(4, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#ifdef LED1_GPIO
/** Start the counter if LED1 is enabled. */
if (g_b_led1_active) {
tc_start(TC0, 0);
}
#else
tc_start(TC0, 0);
#endif
}
void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulDivider, ulTCCLKS;
/* Configure PMC for TC0. */
pmc_enable_periph_clk( ID_TC0 );
/* Configure TC0 channel 0 for interrupts at tmrTIMER_0_FREQUENCY. */
tc_find_mck_divisor( tmrTIMER_0_FREQUENCY, configCPU_CLOCK_HZ, &ulDivider, &ulTCCLKS, configCPU_CLOCK_HZ );
tc_init( TC0, 0, ulTCCLKS | TC_CMR_CPCTRG );
ulDivider <<= 1UL;
tc_write_rc( TC0, 0, ( configCPU_CLOCK_HZ / ulDivider ) / tmrTIMER_0_FREQUENCY );
tc_enable_interrupt( TC0, 0, TC_IER_CPCS );
/* Configure and enable interrupts for both TC0 and TC1, as TC1 interrupts
are manually pended from within the TC0 interrupt handler (see the notes at
the top of this file). */
NVIC_ClearPendingIRQ( TC0_IRQn );
NVIC_ClearPendingIRQ( TC1_IRQn );
NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );
NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
/* Start the timer last of all. */
tc_start( TC0, 0 );
}
int
acpitimer_init(struct acpi_softc *sc)
{
ACPI_STATUS rv;
uint32_t bits;
int i, j;
rv = AcpiGetTimerResolution(&bits);
if (ACPI_FAILURE(rv))
return -1;
if (bits == 32)
acpi_timecounter.tc_counter_mask = 0xffffffff;
for (i = j = 0; i < 10; i++)
j += acpitimer_test();
if (j >= 10) {
acpi_timecounter.tc_name = "ACPI-Fast";
acpi_timecounter.tc_get_timecount = acpitimer_read_fast;
acpi_timecounter.tc_quality = 1000;
}
tc_init(&acpi_timecounter);
aprint_debug_dev(sc->sc_dev, "%s %d-bit timer\n",
acpi_timecounter.tc_name, bits);
return 0;
}
