static void tcc_tsif_isr(struct tcc_tsif_handle *h)
{
volatile PGDMACTRL dma_regs;
if(h->dma_controller == 0)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA0_BASE);
else if(h->dma_controller == 1)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA1_BASE);
else if(h->dma_controller == 2)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA2_BASE);
if(h->dma_ch == 0)
{
if(dma_regs->CHCTRL0.nREG & Hw3) {
BITSET(dma_regs->CHCTRL0.nREG, Hw3); //dma done flag set
h->dma_phy_curpos = dma_regs->C_DADR0.nREG;
}
}
else if(h->dma_ch == 1)
{
if(dma_regs->CHCTRL1.nREG & Hw3) {
BITSET(dma_regs->CHCTRL1.nREG, Hw3); //dma done flag set
h->dma_phy_curpos = dma_regs->C_DADR1.nREG;
}
}
else
{
if(dma_regs->CHCTRL2.nREG & Hw3) {
BITSET(dma_regs->CHCTRL2.nREG, Hw3); //dma done flag set
h->dma_phy_curpos = dma_regs->C_DADR2.nREG;
}
}
h->dma_intr_cnt++;
}
static int tcc_tsif_dmastart(struct tcc_tsif_handle *h)
{
volatile PGDMACTRL dma_regs;
if(h->dma_controller == 0)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA0_BASE);
else if(h->dma_controller == 1)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA1_BASE);
else if(h->dma_controller == 2)
dma_regs = (volatile PGDMACTRL)tcc_p2v(HwGDMA2_BASE);
h->dma_phy_rdpos = h->rx_dma.dma_addr;
h->dma_phy_curpos = h->dma_phy_rdpos;
h->dma_phy_maxaddr = h->dma_phy_curpos + h->dma_total_size;
h->dma_virt_rdpos = (unsigned int)h->rx_dma.v_addr;
h->dma_virt_curpos = h->dma_virt_rdpos;
h->dma_virt_maxaddr = h->dma_virt_curpos + h->dma_total_size;
h->dma_recv_size = 0;
h->dma_intr_cnt = 0;
tcc_tsif_dma_init(h);
if(h->dma_ch == 0) BITSET(dma_regs->CHCTRL0.nREG, Hw0); //dma enable
else if(h->dma_ch == 1) BITSET(dma_regs->CHCTRL1.nREG, Hw0); //dma enable
else BITSET(dma_regs->CHCTRL2.nREG, Hw0); //dma enable
BITSET(h->regs->TSRXCR, Hw31); //tsif enable
#ifdef DEBUG_INFO
printk("%s\n", __func__);
#endif
return 0;
}
static int tcc8800st_mmc_cd_int_config(struct device *dev, int id, unsigned int cd_irq)
{
volatile PPIC pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE);
volatile PGPIO pGPIO = (volatile PGPIO)tcc_p2v(HwGPIO_BASE);
if(id == TCC_MMC_TYPE_SD)
{
BITCSET(pPIC->EI37SEL, 0x00000010, 0x00000010);
BITCSET(pGPIO->EINTSEL1, HwEINTSEL1_EINT4_MASK, HwEINTSEL1_EINT4(SEL_GPIOF13));
}
#if defined(CONFIG_MMC_TCC_PORT7)
else if(id == TCC_MMC_TYPE_WIFI)
{
BITCSET(pPIC->EI37SEL, 0x00000020, 0x00000020);
BITCSET(pGPIO->EINTSEL1, HwEINTSEL1_EINT5_MASK, HwEINTSEL1_EINT5(SEL_GPIOE25));
}
#endif
else
{
}
pPIC->SEL1 |= cd_irq;
pPIC->INTMSK1 |= cd_irq;
pPIC->MODE1 &= (~(cd_irq)); // edge trigger
pPIC->MODEA1 |= (cd_irq); //both edge
pPIC->IEN1 |= cd_irq;
pPIC->CLR1 |= cd_irq;
return 0;
}
int m803_mmc_cd_int_config(struct device *dev, int id, unsigned int cd_irq)
{
volatile PPIC pPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE);
volatile PGPIO pGPIO = (volatile PGPIO)tcc_p2v(HwGPIO_BASE);
if(id == TCC_MMC_TYPE_SD)
{
BITCSET(pPIC->EI37SEL, 0x00000010, 0x00000010);
if(system_rev == 0x0012 || system_rev == 0x0013) // system_rev : 0x0012 = M803 V0.2A
BITCSET(pGPIO->EINTSEL1, HwEINTSEL1_EINT4_MASK, HwEINTSEL1_EINT4(SEL_GPIOE25));
else
BITCSET(pGPIO->EINTSEL1, HwEINTSEL1_EINT4_MASK, HwEINTSEL1_EINT4(SEL_GPIOF17));
}
else
{
return -1;
}
pPIC->SEL1 |= cd_irq;
pPIC->INTMSK1 |= cd_irq;
pPIC->MODE1 &= (~(cd_irq)); // edge trigger
pPIC->MODEA1 |= (cd_irq); //both edge
pPIC->IEN1 |= cd_irq;
pPIC->CLR1 |= cd_irq;
return 0;
}
void tcc_spdif_set_clock(unsigned int clock_rate)
{
unsigned int clk_rate;
unsigned tmpCfg, tmpStatus;
#if defined(CONFIG_ARCH_TCC892X)
volatile ADMASPDIFTX *p_adma_spdif_tx_base = (volatile ADMASPDIFTX *)tcc_p2v(BASE_ADDR_SPDIFTX1);
#else
volatile ADMASPDIFTX *p_adma_spdif_tx_base = (volatile ADMASPDIFTX *)tcc_p2v(BASE_ADDR_SPDIFTX);
#endif
#if defined(CONFIG_MEM_CLK_SYNC_MODE)
unsigned int pll3_rate;
volatile PCKC pCKC = (volatile PCKC)tcc_p2v(HwCKC_BASE);
#endif
alsa_dbg("[%s], clock_rate[%u]\n", __func__, clock_rate);
//clk_rate = ((clock_rate * 256 * 2) / 100);
clk_rate = io_ckc_get_dai_clock(clock_rate) * 2; /* set 512fs for HDMI */
#if defined(CONFIG_MEM_CLK_SYNC_MODE)
if ((pCKC->MBUSCTRL & 0x1) == 0) {
if (clock_rate == 44100)
pll3_rate = 429*1000*1000;
else if (clock_rate == 48000)
pll3_rate = 639*1000*1000;
else if (clock_rate == 32000)
pll3_rate = 213*1000*1000;
else if (clock_rate == 22000)
pll3_rate = 429*1000*1000;
else if (clock_rate == 11000)
pll3_rate = 604*1000*1000;
else
pll3_rate = 429*1000*1000;
clk_set_rate(tcc_spdif_clk, 1000000);
clk_set_rate(pll3_clk, pll3_rate);
}
#endif
clk_set_rate(tcc_spdif_clk, clk_rate);
tmpCfg = p_adma_spdif_tx_base->TxConfig;
tmpStatus = p_adma_spdif_tx_base->TxChStat;
if (clock_rate == 44100) { /* 44.1KHz */
p_adma_spdif_tx_base->TxConfig = ((tmpCfg & 0xFFFF00FF) | (2 << 8));
p_adma_spdif_tx_base->TxChStat = ((tmpStatus & 0xFFFFFF3F) | (0 << 6));
} else if (clock_rate == 48000) { /* 48KHz */
p_adma_spdif_tx_base->TxConfig = ((tmpCfg & 0xFFFF00FF) | (2 << 8));
p_adma_spdif_tx_base->TxChStat = ((tmpStatus & 0xFFFFFF3F) | (1 << 6));
} else if (clock_rate == 32000) { /* 32KHz */
p_adma_spdif_tx_base->TxConfig = ((tmpCfg & 0xFFFF00FF) | (2 << 8));
p_adma_spdif_tx_base->TxChStat = ((tmpStatus & 0xFFFFFF3F) | (2 << 6));
} else { /* Sampling Rate Converter */
p_adma_spdif_tx_base->TxConfig = ((tmpCfg & 0xFFFF00FF) | (2 << 8));
p_adma_spdif_tx_base->TxChStat = ((tmpStatus & 0xFFFFFF3F) | (3 << 6));
}
}
void tchal_init(void)
{
#ifdef __USE_TC_CPU__
tcbd_debug(DEBUG_TCHAL, "\n");
RGPIO = (PGPIO)tcc_p2v(HwGPIO_BASE);
RPIC = (PPIC)tcc_p2v(HwPIC_BASE);
#endif
tchal_power_down_device();
}
static void tcc_tsif_isr(struct tcc_tsif_handle *h)
{
volatile PTSIFDMA dma_regs;
unsigned long dma_done_reg = 0;
if(h->id == 0) dma_regs = (volatile PTSIFDMA)tcc_p2v(HwTSIF_DMA0_BASE);
else if(h->id == 1) dma_regs = (volatile PTSIFDMA)tcc_p2v(HwTSIF_DMA1_BASE);
else dma_regs = (volatile PTSIFDMA)tcc_p2v(HwTSIF_DMA2_BASE);
dma_done_reg = dma_regs->DMAICR.nREG;
if(dma_done_reg & (Hw29|Hw28)) {
BITSET(dma_regs->DMAICR.nREG, (Hw29|Hw28));
h->cur_q_pos = (int)(dma_regs->DMASTR.nREG >> 17);
}
/************************************************************************
* Local Function
************************************************************************/
static int tcc_i2s_init(void)
{
#if defined(CONFIG_ARCH_TCC892X)
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI0);
alsa_dbg(" %s \n", __func__);
/* clock enable */
tcc_dai_clk = clk_get(NULL, CLK_NAME_DAI0);
if(IS_ERR(tcc_dai_clk)) return (-EINVAL);
clk_enable(tcc_dai_clk);
tcc_adma0_clk = clk_get(NULL, CLK_NAME_ADMA0);
if(IS_ERR(tcc_adma0_clk)) return (-EINVAL);
clk_enable(tcc_adma0_clk);
#else
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI);
volatile PPIC pPIC = (volatile PPIC)tcc_p2v(BASE_ADDR_PIC);
alsa_dbg(" %s \n", __func__);
/* clock enable */
tcc_dai_clk = clk_get(NULL, CLK_NAME_DAI);
if(IS_ERR(tcc_dai_clk)) return (-EINVAL);
clk_enable(tcc_dai_clk);
tcc_adma_clk = clk_get(NULL, CLK_NAME_ADMA);
if(IS_ERR(tcc_adma_clk)) return (-EINVAL);
clk_enable(tcc_adma_clk);
#endif
#if defined(CONFIG_MEM_CLK_SYNC_MODE)
if (pll3_clk == NULL) {
pll3_clk = clk_get(NULL, "pll3");
if (IS_ERR(pll3_clk)) return (-EINVAL);
}
#endif
/* set DAI register */
tca_i2s_dai_init(pADMA_DAI);
BITSET(pADMA_DAI->MCCR0, Hw31 | Hw30 | Hw29 | Hw28);
tca_i2s_stop(pADMA_DAI, AMDA_RX); // ADMA Rx disable
tca_i2s_stop(pADMA_DAI, AMDA_TX); // ADMA Tx disable
return 0;
}
/*------------------------------------------------------------------
Gre2d_SetFCh_Chroma_key
graphic engine Front channel chroma key Set
-------------------------------------------------------------------*/
void Gre2d_SetFCh_Chroma_key(G2D_CHANNEL ch, unsigned char RY, unsigned char GU, unsigned char BV)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
switch(ch)
{
case FCH0_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->S0_CHROMA.nREG,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF))); // pHwOVERLAYMIXER->S0_CHROMA
#else
BITCSET(pHwOVERLAYMIXER->S0_CHROMA,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF))); // pHwOVERLAYMIXER->S0_CHROMA
#endif
break;
case FCH1_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->S1_CHROMA.nREG,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF))); // pHwOVERLAYMIXER->S0_CHROMA
#else
BITCSET(pHwOVERLAYMIXER->S1_CHROMA,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF)));
#endif
break;
case FCH2_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->S2_CHROMA.nREG,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF))); // pHwOVERLAYMIXER->S0_CHROMA
#else
BITCSET(pHwOVERLAYMIXER->S2_CHROMA,0x00FFFFFF, (((RY<<16)&0xFF0000) | ((GU<<8)&0xFF00)| (BV&0xFF)));
#endif
break;
default:
break;
}
}
void Gre2d_Grp_Clut_Ctrl(unsigned int ch, unsigned int index, unsigned int data)
{
OVERLAYMIXER *p;
unsigned int *pClut;
if(index > 256)
{
printk("[%s:%d] Invalid index value(%d)\n",__func__, __LINE__, index);
return;
}
p = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
if(ch== 0){
pClut = (unsigned int*)&p->FCH0_LUT[0];
pClut[index] = data;
}
else if(ch == 1){
pClut = (unsigned int*)&p->FCH1_LUT[0];
pClut[index] = data;
}
else if(ch == 2){
pClut = (unsigned int*)&p->FCH2_LUT[0];
pClut[index] = data;
}
else {
printk("[%s:%d] invalid ch for clut\n", __func__, __LINE__);
}
}
void Gre2d_operator_ctrl(G2D_OP_TYPE op_set, G2D_OP_ACON ACON1, G2D_OP_ACON ACON0, G2D_OP_CCON CCON1, G2D_OP_CCON CCON0, G2D_OP_ATUNE ATUNE, G2D_OP1_CHROMA CSEL,GE_ROP_TYPE op )
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
switch(op_set){
case OP_0:
BITCSET(pHwOVERLAYMIXER->OP0_CTRL.nREG, 0xFFFFFFFF, ( ( (ACON1<<28)&HwGE_OP_CTRL_ACON1)| ((ACON0<<24)&HwGE_OP_CTRL_ACON0)
| ( (CCON1<<21)&HwGE_OP_CTRL_CCON1)| ((CCON0<<16)&HwGE_OP_CTRL_CCON0)
| ( (ATUNE<<12)&HwGE_OP_CTRL_ATUNE)| ((CSEL<<8)&HwGE_OP_CTRL_CSEL)
| (op & HwGE_OP_CTRL_OPMODE)));
break;
case OP_1:
BITCSET(pHwOVERLAYMIXER->OP1_CTRL.nREG, 0xFFFFFFFF, ( ( (ACON1<<28)&HwGE_OP_CTRL_ACON1)| ((ACON0<<24)&HwGE_OP_CTRL_ACON0)
| ( (CCON1<<21)&HwGE_OP_CTRL_CCON1)| ((CCON0<<16)&HwGE_OP_CTRL_CCON0)
| ( (ATUNE<<12)&HwGE_OP_CTRL_ATUNE)| ((CSEL<<8)&HwGE_OP_CTRL_CSEL)
| (op & HwGE_OP_CTRL_OPMODE)));
break;
case OP_2:
BITCSET(pHwOVERLAYMIXER->OP2_CTRL.nREG, 0xFFFFFFFF, ( ( (ACON1<<28)&HwGE_OP_CTRL_ACON1)| ((ACON0<<24)&HwGE_OP_CTRL_ACON0)
| ( (CCON1<<21)&HwGE_OP_CTRL_CCON1)| ((CCON0<<16)&HwGE_OP_CTRL_CCON0)
| ( (ATUNE<<12)&HwGE_OP_CTRL_ATUNE)| ((CSEL<<8)&HwGE_OP_CTRL_CSEL)
| (op & HwGE_OP_CTRL_OPMODE)));
break;
default:
break;
}
}
/*------------------------------------------------------------------
Gre2d_SetBCh_control
graphic engine Back END channel control setting
ysel, xsel:
converter_en : format converter enable RGB -> YUV
converter_mode : format converter mode RGB -> YUV
opmode : flip, rotate
data_form : rgb, yuv, alpha-rgb
-------------------------------------------------------------------*/
void Gre2d_SetBCh_control(G2D_BCH_CTRL_TYPE *reg)
{
unsigned int BCH_ctrl_reg = 0;
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
BCH_ctrl_reg |= ((reg->MABC<<21) & HwGE_BCH_DCTRL_MABC);
BCH_ctrl_reg |= ((reg->ysel<<18) & HwGE_BCH_DCTRL_YSEL);
BCH_ctrl_reg |= ((reg->xsel<<16) & HwGE_BCH_DCTRL_XSEL);
BCH_ctrl_reg |= ((reg->converter_en<<15) & HwGE_BCH_DCTRL_CEN);
BCH_ctrl_reg |= ((reg->converter_mode<<13) & HwGE_BCH_DCTRL_CMODE);
BCH_ctrl_reg |= ((reg->DSUV<<11) & HwGE_BCH_DCTRL_DSUV);
BCH_ctrl_reg |= ((reg->opmode<<8) & HwGE_BCH_DCTRL_OPMODE);
BCH_ctrl_reg |= ((reg->dithering_type<<6) & HwGE_BCH_DCTRL_DOP);
BCH_ctrl_reg |= ((reg->dithering_en<<5) & HwGE_BCH_DCTRL_DEN);
BCH_ctrl_reg |= (reg->data_form.format & HwGE_BCH_DCTRL_DDFRM);
#if !defined(CONFIG_ARCH_TCC92XX)
BCH_ctrl_reg |= ((reg->data_form.data_swap<<24) & HwGE_DCH_SSB);
#endif//
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->BCH_DCTRL.nREG, 0xFFFFFFFFF, BCH_ctrl_reg); // pHwOVERLAYMIXER->BCH_DCTRL
#else
BITCSET(pHwOVERLAYMIXER->BCH_DCTRL, 0xFFFFFFFFF, BCH_ctrl_reg); // pHwOVERLAYMIXER->BCH_DCTRL
#endif
}
/**********************************************************
*
* Function of
*
*
* Input :
* Output :
* Return :
*
* Description :
**********************************************************/
void CIF_WaitFrameSync(unsigned int exp_timer)
{
unsigned int cnt=0;
#ifdef CONFIG_ARCH_TCC79X
while((HwCIRQ & HwCIRQ_SOF) != HwCIRQ_SOF)
{
mdelay(1);
cnt++;
if(cnt>exp_timer)
return;
}
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add
#else //CONFIG_ARCH_TCC92XX
PCIF pCIF = (PCIF)tcc_p2v(HwCIF_BASE);
while((pCIF->CIRQ & HwCIRQ_SOF) != HwCIRQ_SOF)
{
mdelay(1);
cnt++;
if(cnt>exp_timer)
return;
}
#endif
}
/**********************************************************
*
* Function of
*
*
*
* Input :
* Output :
* Return :
*
* Description :
**********************************************************/
void CIF_ONOFF(unsigned int uiOnOff)
{
#ifdef CONFIG_ARCH_TCC79X
if(uiOnOff == ON)
{
BITCSET(HwICPCR1, HwICPCR1_ON, (uiOnOff << 31));
}
else if(uiOnOff == OFF)
{
BITCSET(HwICPCR1, HwICPCR1_ON, (uiOnOff << 31));
}
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add.
#else //CONFIG_ARCH_TCC92XX
volatile PCIF pCIF = (PCIF)tcc_p2v(HwCIF_BASE);
if(uiOnOff == ON)
{
BITCSET(pCIF->ICPCR1, HwICPCR1_ON, (uiOnOff << 31));
}
else if(uiOnOff == OFF)
{
BITCSET(pCIF->ICPCR1, HwICPCR1_ON, (uiOnOff << 31));
}
#endif
}
/*****************************************************************************
* Function Name : tca_i2c_setgpio(int ch)
* Description: I2C port configuration
* input parameter:
* int core; // I2C Core
* int ch; // I2C master channel
******************************************************************************/
void tca_i2c_setgpio(int core, int ch)
{
PGPIO gpio = (PGPIO)tcc_p2v(HwGPIO_BASE);
switch (core) {
case 0:
{
if (ch == 0) {
BITCSET(gpio->GPAFN0, (Hw8-Hw0), Hw4|Hw0); /* GPIO_A[1:0] */
BITSET(gpio->GPAEN, Hw1|Hw0);
BITCLR(gpio->GPADAT, Hw1|Hw0);
} else if (ch == 1) {
BITCSET(gpio->GPAFN0, (Hw32-Hw28), Hw28); /* GPIO_A[7] */
BITCSET(gpio->GPAFN1, (Hw4-Hw0), Hw0); /* GPIO_A[8] */
BITSET(gpio->GPAEN, Hw8|Hw7);
BITCLR(gpio->GPADAT, Hw8|Hw7);
}
break;
}
case 1:
{
if (ch == 0) {
/* Not used */
} else if (ch == 1) {
/* Not used */
}
break;
}
}
}
void CIF_OpStop(char wait_SOF, char sw_reset )
{
#if defined(CONFIG_ARCH_TCC79X)
if(wait_SOF)
{
BITSET(HwCIF->CIRQ, HwCIRQ_SOF);
CIF_WaitFrameSync(400);
BITSET(HwCIF->CIRQ, HwCIRQ_SOF);
}
#elif defined(CONFIG_ARCH_TCC92XX) || defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
volatile PCIF pCIF = (PCIF)tcc_p2v(HwCIF_BASE);
#if defined(CONFIG_ARCH_TCC92XX)
volatile PDDICONFIG pDDICfg = (PDDICONFIG)tcc_p2v(HwDDI_CONFIG_BASE);
#elif defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
volatile PCAMBUSCFG pCamBusCfg = (PCAMBUSCFG)tcc_p2v(HwCAMBUSCFG_BASE);
#endif
if(wait_SOF)
{
BITSET(pCIF->CIRQ, HwCIRQ_SOF);
CIF_WaitFrameSync(400);
BITSET(pCIF->CIRQ, HwCIRQ_SOF);
}
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add.
#endif
CIF_ONOFF(OFF);
if(sw_reset)
{
#if defined(CONFIG_ARCH_TCC79X)
BITSET(HwSWRESET, HwSWRESET_CIC_ON);
BITCLR(HwSWRESET, HwSWRESET_CIC_ON);
#elif defined(CONFIG_ARCH_TCC92XX)
BITSET(pDDICfg->SWRESET, HwDDIC_SWRESET_CIF); // Reset
BITCLR(pDDICfg->SWRESET, HwDDIC_SWRESET_CIF); // Normal
#elif defined(CONFIG_ARCH_TCC93XX) || defined(CONFIG_ARCH_TCC88XX)
BITSET(pCamBusCfg->SoftResetRegister, HwCAMBUS_SWRESET_CIF); // Reset
BITCLR(pCamBusCfg->SoftResetRegister, HwCAMBUS_SWRESET_CIF); // Normal
#elif defined(CONFIG_ARCH_TCC892X)
// In case of 892X, we have to add.
#endif
}
}
void VIOC_DISP_SWReset( unsigned int DISP )
{
volatile PVIOC_IREQ_CONFIG pIREQConfig;
pIREQConfig = (volatile PVIOC_IREQ_CONFIG)tcc_p2v((unsigned int)HwVIOC_IREQ);
BITCSET(pIREQConfig->uSOFTRESET.nREG[1], (0x1<<(20+DISP)), (0x1<<(20+DISP))); // disp reset
BITCSET(pIREQConfig->uSOFTRESET.nREG[1], (0x1<<(20+DISP)), (0x0<<(20+DISP))); // disp reset
}
void Gre2d_operator_ctrl(G2D_ASEL_TYPE ASEL1, G2D_OP1_CHROMA CSEL1, GE_ROP_TYPE op1, G2D_ASEL_TYPE ASEL0, G2D_OP0_CHROMA CSEL0, GE_ROP_TYPE op0)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
BITCSET(pHwOVERLAYMIXER->OP_CTRL, 0x01FF01FF, (((ASEL1<<23)&HwGE_OP_CTRL_ASEL1)| ((CSEL1<<21)&HwGE_OP_CTRL_CSEL1) | ((op1<<16) & HwGE_OP_CTRL_OP1_MODE)
|((ASEL0<<7)&HwGE_OP_CTRL_ASEL0)| ((CSEL0<<5)&HwGE_OP_CTRL_CSEL0) | (op0 & HwGE_OP_CTRL_OP0_MODE)));
}
static int tcc_i2s_suspend(struct snd_soc_dai *dai)
{
#if defined(CONFIG_ARCH_TCC892X)
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI0);
volatile PADMASPDIFTX pADMA_SPDIFTX = (volatile PADMASPDIFTX)tcc_p2v(BASE_ADDR_SPDIFTX0);
#else
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI);
volatile PADMASPDIFTX pADMA_SPDIFTX = (volatile PADMASPDIFTX)tcc_p2v(BASE_ADDR_SPDIFTX);
#endif
alsa_dbg(" %s \n", __func__);
if(dai->id == 0) { // DAI
gADMA_DAI.DAMR = pADMA_DAI->DAMR;
gADMA_DAI.DAVC = pADMA_DAI->DAVC;
gADMA_DAI.MCCR0 = pADMA_DAI->MCCR0;
gADMA_DAI.MCCR1 = pADMA_DAI->MCCR1;
if(tcc_dai_clk)
clk_disable(tcc_dai_clk);
#if defined(CONFIG_ARCH_TCC892X)
if(tcc_adma0_clk)
clk_disable(tcc_adma0_clk);
#else
if(tcc_adma_clk)
clk_disable(tcc_adma_clk);
#endif
}
else { // SPDIFTX
gADMA_SPDIFTX.TxConfig = pADMA_SPDIFTX->TxConfig;
gADMA_SPDIFTX.TxChStat = pADMA_SPDIFTX->TxChStat;
gADMA_SPDIFTX.TxIntMask = pADMA_SPDIFTX->TxIntMask;
// gADMA_SPDIFTX.TxIntStat = pADMA_SPDIFTX->TxIntStat;
gADMA_SPDIFTX.DMACFG = pADMA_SPDIFTX->DMACFG;
if(tcc_spdif_clk)
clk_disable(tcc_spdif_clk);
#if defined(CONFIG_ARCH_TCC892X)
if(tcc_adma1_clk)
clk_disable(tcc_adma1_clk);
#endif
}
return 0;
}
static int tcc_i2s_resume(struct snd_soc_dai *dai)
{
#if defined(CONFIG_ARCH_TCC892X)
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI0);
volatile PADMASPDIFTX pADMA_SPDIFTX = (volatile PADMASPDIFTX)tcc_p2v(BASE_ADDR_SPDIFTX1);
#else
volatile PADMADAI pADMA_DAI = (volatile PADMADAI)tcc_p2v(BASE_ADDR_DAI);
volatile PADMASPDIFTX pADMA_SPDIFTX = (volatile PADMASPDIFTX)tcc_p2v(BASE_ADDR_SPDIFTX);
#endif
alsa_dbg(" %s \n", __func__);
if(dai->id == 0) { // DAI
if(tcc_dai_clk)
clk_enable(tcc_dai_clk);
#if defined(CONFIG_ARCH_TCC892X)
if(tcc_adma0_clk)
clk_enable(tcc_adma0_clk);
#else
if(tcc_adma_clk)
clk_enable(tcc_adma_clk);
#endif
pADMA_DAI->DAMR = gADMA_DAI.DAMR;
pADMA_DAI->DAVC = gADMA_DAI.DAVC;
pADMA_DAI->MCCR0 = gADMA_DAI.MCCR0;
pADMA_DAI->MCCR1 = gADMA_DAI.MCCR1;
}
else { // SPDIFTX
if(tcc_spdif_clk)
clk_enable(tcc_spdif_clk);
#if defined(CONFIG_ARCH_TCC892X)
if(tcc_adma1_clk)
clk_enable(tcc_adma1_clk);
#endif
pADMA_SPDIFTX->TxConfig = gADMA_SPDIFTX.TxConfig;
pADMA_SPDIFTX->TxChStat = gADMA_SPDIFTX.TxChStat;
pADMA_SPDIFTX->TxIntMask = gADMA_SPDIFTX.TxIntMask;
// pADMA_SPDIFTX->TxIntStat = gADMA_SPDIFTX.TxIntStat;
pADMA_SPDIFTX->DMACFG = gADMA_SPDIFTX.DMACFG;
}
return 0;
}
/*****************************************************************************
* Function Name : static void Init_IR_Port(void);
* Description : IR port register init
* Arguments :
******************************************************************************/
static void Init_IR_Port(void)
{
#if defined(CONFIG_ARCH_TCC892X)
tcc_gpio_config(TCC_GPG(17), GPIO_FN7|GPIO_OUTPUT|GPIO_LOW);
#else
PGPIO pGpioA = (volatile PGPIO)tcc_p2v(HwGPIOA_BASE);
BITCSET(pGpioA->GPAFN0, (Hw20 | Hw21 | Hw22 | Hw23), Hw20); //GPIO_A5
#endif
}
void VIOC_SC_IreqHandler(int index, int irq, void *client_data)
{
//unsigned int idx = 0; // temp value.
volatile PVIOC_SC pScaler;
pScaler = (volatile PVIOC_SC)tcc_p2v((unsigned int)HwVIOC_SC0 + index*0x100);
#if 0
if(vectorID > VIOC_IREQ_MAX)
return;
idx = vectorID - VIOC_IREQ_SC0;
#endif
if(pScaler->uSTATUS.nREG & VIOC_SC_IREQ_UPDDONE_MASK && pScaler->uIRQMSK.bREG.UPDDONE == 0)
{
/* Interrput Source Clear */
/* Status Clear */
pScaler->uSTATUS.bREG.UPDDONE = 1;
/* DO Action for Interrupt */
/* Interrput Re-Setting */
}
if(pScaler->uSTATUS.nREG & VIOC_SC_IREQ_EOFRISE_MASK && pScaler->uIRQMSK.bREG.EOFRISE == 0)
{
/* Interrput Source Clear */
/* Status Clear */
pScaler->uSTATUS.bREG.EOFRISE = 1;
/* DO Action for Interrupt */
/* Interrput Re-Setting */
}
if(pScaler->uSTATUS.nREG & VIOC_SC_IREQ_EOFFALL_MASK && pScaler->uIRQMSK.bREG.EOFFALL == 0)
{
/* Interrput Source Clear */
/* Status Clear */
pScaler->uSTATUS.bREG.EOFFALL = 1;
/* DO Action for Interrupt */
/* Interrput Re-Setting */
}
if(pScaler->uSTATUS.nREG & VIOC_SC_IREQ_ERROR_MASK && pScaler->uIRQMSK.bREG.ERR == 0)
{
/* Interrput Source Clear */
/* Status Clear */
pScaler->uSTATUS.bREG.ERR = 1;
/* DO Action for Interrupt */
/* Interrput Re-Setting */
}
}
/*------------------------------------------------------------------
Gre2d_src_ctrl
graphic engine sorce control
-------------------------------------------------------------------*/
void Gre2d_src_ctrl(G2D_SRC_CTRL reg)
{
unsigned int sf_ctrl_reg = 0, sa_ctrl_reg = 0,ctrl_reg = 0;
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
#if defined(CONFIG_ARCH_TCC892X)
// source YUV to RGB converter enable sf_ctrl
sf_ctrl_reg |= (((reg.src0_y2r.src_y2r <<24) & Hw2D_SFCTRL_S0_Y2REN) |
((reg.src1_y2r.src_y2r <<25) & Hw2D_SFCTRL_S1_Y2REN) | ((reg.src2_y2r.src_y2r <<26) & Hw2D_SFCTRL_S2_Y2REN));
// source YUV to RGB coverter type sf_ctrl
sf_ctrl_reg |= (((reg.src0_y2r.src_y2r_type<<16) & Hw2D_SFCTRL_S0_Y2RMODE) |
((reg.src1_y2r.src_y2r_type <<18) & Hw2D_SFCTRL_S1_Y2RMODE) | ((reg.src2_y2r.src_y2r_type <<20) & Hw2D_SFCTRL_S2_Y2RMODE));
// source select sf_ctrl
sf_ctrl_reg |= ((reg.src_sel_0) & Hw2D_SFCTRL_S0_SEL) |((reg.src_sel_1<<2) & Hw2D_SFCTRL_S1_SEL)
| ((reg.src_sel_2<<4) & Hw2D_SFCTRL_S2_SEL) | ((reg.src_sel_3<<6) & Hw2D_SFCTRL_S3_SEL) ;
// source arithmetic mode sa_ctrl
sa_ctrl_reg |= (((reg.src0_arith ) & Hw2D_SACTRL_S0_ARITHMODE) |
((reg.src1_arith<<4) & Hw2D_SACTRL_S1_ARITHMODE) | ((reg.src2_arith<<8) & Hw2D_SACTRL_S2_ARITHMODE));
// source chroma key enable : for arithmetic sa_ctrl
sa_ctrl_reg |= (((reg.src0_chroma_en<<16) & Hw2D_SACTRL_S0_CHROMAEN) |
((reg.src1_chroma_en<<17) & Hw2D_SACTRL_S1_CHROMAEN) | ((reg.src2_chroma_en<<18) & Hw2D_SACTRL_S2_CHROMAEN));
BITCSET(pHwOVERLAYMIXER->SF_CTRL.nREG, 0x0FFFFFFF, sf_ctrl_reg);
BITCSET(pHwOVERLAYMIXER->SA_CTRL.nREG, 0x0FFFFFFF, sa_ctrl_reg);
#else
// source arithmetic mode
ctrl_reg |= (((reg.src0_arith<<19) & Hw2D_SCTRL_S0_ARITHMODE) |
((reg.src1_arith<<22) & Hw2D_SCTRL_S1_ARITHMODE) | ((reg.src2_arith<<25) & Hw2D_SCTRL_S2_ARITHMODE));
// source YUV to RGB converter enable
ctrl_reg |= (((reg.src0_y2r.src_y2r <<16) & Hw2D_SCTRL_S0_Y2REN) |
((reg.src1_y2r.src_y2r <<17) & Hw2D_SCTRL_S1_Y2REN) | ((reg.src2_y2r.src_y2r <<18) & Hw2D_SCTRL_S2_Y2REN));
// source YUV to RGB coverter type
ctrl_reg |= (((reg.src0_y2r.src_y2r_type<<9) & Hw2D_SCTRL_S0_Y2RMODE) |
((reg.src1_y2r.src_y2r_type <<11) & Hw2D_SCTRL_S1_Y2RMODE) | ((reg.src2_y2r.src_y2r_type <<13) & Hw2D_SCTRL_S2_Y2RMODE));
// source chroma key enable : for arithmetic
ctrl_reg |= (((reg.src0_chroma_en<<6) & Hw2D_SCTRL_S0_CHROMAEN) |
((reg.src1_chroma_en<<7) & Hw2D_SCTRL_S1_CHROMAEN) | ((reg.src2_chroma_en<<8) & Hw2D_SCTRL_S2_CHROMAEN));
// source select
ctrl_reg |= (((reg.src_sel_0) & Hw2D_SCTRL_S0_SEL) |
((reg.src_sel_1<<2) & Hw2D_SCTRL_S1_SEL) | ((reg.src_sel_2<<4) & Hw2D_SCTRL_S2_SEL));
BITCSET(pHwOVERLAYMIXER->S_CTRL, 0x0FFFFFFF, ctrl_reg);
#endif
}
void internal_tve_enable(unsigned int type, unsigned int onoff)
{
volatile PNTSCPAL pHwTVE = (volatile PNTSCPAL)tcc_p2v(HwTVE_BASE);
volatile PNTSCPAL_ENCODER_CTRL pHwTVE_VEN = (volatile PNTSCPAL_ENCODER_CTRL)tcc_p2v(HwNTSCPAL_ENC_CTRL_BASE);
if(onoff)
{
internal_tve_set_config(type);
BITSET(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN);
BITSET(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN);
BITCLR(pHwTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD);
}
else
{
BITCLR(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN);
BITCLR(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN);
BITSET(pHwTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD);
}
}
/*****************************************************************************
Function Name : tcc_composite_ext_handler()
******************************************************************************/
static irqreturn_t tcc_composite_ext_handler(int irq, void *dev_id)
{
#if defined(CONFIG_MACH_TCC9300ST) || defined(CONFIG_MACH_TCC8800ST)
PPIC pHwPIC = (volatile PPIC)tcc_p2v(HwVPIC_BASE);
#elif defined(CONFIG_MACH_TCC8920ST)
PPIC pHwPIC = (volatile PPIC)tcc_p2v(HwPIC_BASE);
#endif
dprintk("%s, composite_plugout_count=%d\n", __func__, composite_plugout_count);
composite_plugout_count++;
if(composite_plugout_count > 10)
{
composite_plugout_count = 0;
composite_plugout = 1;
#if defined(CONFIG_MACH_TCC9300ST)
BITCLR(pHwPIC->INTMSK0, COMPOSITE_DETECT_EINT);
BITCLR(pHwPIC->IEN0, COMPOSITE_DETECT_EINT);
BITSET(pHwPIC->CLR0, COMPOSITE_DETECT_EINT);
#elif defined(CONFIG_MACH_TCC8800ST)
BITCLR(pHwPIC->INTMSK1, COMPOSITE_DETECT_EINT);
BITCLR(pHwPIC->IEN1, COMPOSITE_DETECT_EINT);
BITSET(pHwPIC->CLR1, COMPOSITE_DETECT_EINT);
#elif defined(CONFIG_MACH_TCC8920ST)
BITCLR(pHwPIC->INTMSK0.nREG, COMPOSITE_DETECT_EINT);
BITCLR(pHwPIC->IEN0.nREG, COMPOSITE_DETECT_EINT);
BITSET(pHwPIC->CLR0.nREG, COMPOSITE_DETECT_EINT);
#endif
}
else
{
#if defined(CONFIG_MACH_TCC9300ST)
BITSET(pHwPIC->CLR0, COMPOSITE_DETECT_EINT);
#elif defined(CONFIG_MACH_TCC8800ST)
BITSET(pHwPIC->CLR1, COMPOSITE_DETECT_EINT);
#elif defined(CONFIG_MACH_TCC8920ST)
BITSET(pHwPIC->CLR0.nREG, COMPOSITE_DETECT_EINT);
#endif
}
return IRQ_HANDLED;
}
/*------------------------------------------------------------------
Gre2d_SetFCh_position
graphic engine Front channel position settig
frameps_x, frameps_y : frame pixsel size
poffset_x, poffset_y : pixsel offset
imageps_x, imageps_y : imagme pixel size
winps_x, winps_y : window pixsel offset
-------------------------------------------------------------------*/
void Gre2d_SetFCh_position(G2D_CHANNEL ch, unsigned int frameps_x, unsigned int frameps_y,
unsigned int poffset_x, unsigned int poffset_y, unsigned int imageps_x, unsigned int imageps_y, unsigned int winps_x, unsigned int winps_y )
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
switch(ch)
{
case FCH0_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH0_SFSIZE.nREG,0x0FFF0FFF,((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->FCH0_SFSIZE
BITCSET(pHwOVERLAYMIXER->FCH0_SOFF.nREG,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH0_SISIZE.nREG,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH0_WOFF.nREG,0x0FFF0FFF,((winps_y<<16) | winps_x));
#else
BITCSET(pHwOVERLAYMIXER->FCH0_SFSIZE,0x0FFF0FFF,((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->FCH0_SFSIZE
BITCSET(pHwOVERLAYMIXER->FCH0_SOFF,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH0_SISIZE,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH0_WOFF,0x0FFF0FFF,((winps_y<<16) | winps_x));
#endif
break;
case FCH1_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH1_SFSIZE.nREG,0x0FFF0FFF,((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->FCH0_SFSIZE
BITCSET(pHwOVERLAYMIXER->FCH1_SOFF.nREG,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH1_SISIZE.nREG,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH1_WOFF.nREG,0x0FFF0FFF,((winps_y<<16) | winps_x));
#else
BITCSET(pHwOVERLAYMIXER->FCH1_SFSIZE,0x0FFF0FFF,((frameps_y<<16) | frameps_x));
BITCSET(pHwOVERLAYMIXER->FCH1_SOFF,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH1_SISIZE,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH1_WOFF,0x0FFF0FFF,((winps_y<<16) | winps_x));
#endif
break;
case FCH2_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH2_SFSIZE.nREG,0x0FFF0FFF,((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->FCH0_SFSIZE
BITCSET(pHwOVERLAYMIXER->FCH2_SOFF.nREG,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH2_SISIZE.nREG,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH2_WOFF.nREG,0x0FFF0FFF,((winps_y<<16) | winps_x));
#else
BITCSET(pHwOVERLAYMIXER->FCH2_SFSIZE,0x0FFF0FFF,((frameps_y<<16) | frameps_x));
BITCSET(pHwOVERLAYMIXER->FCH2_SOFF,0x0FFF0FFF,((poffset_y<<16) | poffset_x));
BITCSET(pHwOVERLAYMIXER->FCH2_SISIZE,0x0FFF0FFF,((imageps_y<<16) | imageps_x));
BITCSET(pHwOVERLAYMIXER->FCH2_WOFF,0x0FFF0FFF,((winps_y<<16) | winps_x));
#endif
break;
default:
break;
}
}
static int gpio_event_resume(struct platform_device *pdev)
{
#if 0 //Often does not wakeup in user mode. so, has commented. - 120303, hjbae
int is_wakeup_by_powerkey = 0;
PPMU pPMU = (PPMU)tcc_p2v(HwPMU_BASE);
#if defined(CONFIG_REGULATOR_AXP192_PEK) || defined(CONFIG_REGULATOR_AXP202_PEK)
return 0;
#endif
// WKUP from PowerKey & PowerKey is not pressed.
#if defined(CONFIG_MACH_M805_892X)
if (system_rev == 0x2002 || system_rev == 0x2003 || system_rev == 0x2004 || system_rev == 0x2005)
{
if((pPMU->PMU_WKSTS1.bREG.GPIO_E15)&&(gpio_get_value(TCC_GPE(15))))
is_wakeup_by_powerkey = 1;
}
else
{
if((pPMU->PMU_WKSTS0.bREG.GPIO_D09)&&(gpio_get_value(TCC_GPD(9))))
is_wakeup_by_powerkey = 1;
}
#elif defined(CONFIG_MACH_TCC8920ST)
if((pPMU->PMU_WKSTS0.bREG.GPIO_D14)&&(gpio_get_value(TCC_GPD(14))))
is_wakeup_by_powerkey = 1;
#elif defined(CONFIG_ARCH_TCC892X)
if(system_rev == 0x1005 || system_rev == 0x1007 || system_rev == 0x1008)
{
if((pPMU->PMU_WKSTS1.bREG.GPIO_E30)&&(gpio_get_value(TCC_GPE(30))))
is_wakeup_by_powerkey = 1;
}
else if(system_rev == 0x1006)
{
if((pPMU->PMU_WKSTS1.bREG.GPIO_E24)&&(gpio_get_value(TCC_GPE(24))))
is_wakeup_by_powerkey = 1;
}
else
{
if((pPMU->PMU_WKSTS0.bREG.GPIO_G16)&&(gpio_get_value(TCC_GPG(16))))
is_wakeup_by_powerkey = 1;
}
#endif
if (is_wakeup_by_powerkey == 1) {
cancel_delayed_work(&work);
if (event_dev)
input_report_key(event_dev, KEY_POWER, 1); //KEY_END
queue_delayed_work(event_wq, &work, msecs_to_jiffies(100));
printk("[Wakeup by Short PowerKey!!!]\n");
}
#endif
return 0;
}
static void __init tcc88xx_timer_init(void)
{
unsigned long rate;
rate = TCC_TIMER_FREQ;
pTIMER = (volatile PTIMER) tcc_p2v(HwTMR_BASE);
pPIC = (volatile PPIC) tcc_p2v(HwPIC_BASE);
pTIMER->TC32EN = 1; /* Timer disable, Prescale is one */
BITSET(pTIMER->TC32EN, Hw24); /* Timer Enable */
if (pTIMER->TC32IRQ & Hw31) /* IRQ clear */
BITSET(pTIMER->TC32IRQ, Hw31);
ckevt_tcc88xx_osmr0.mult =
div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_tcc88xx_osmr0.shift);
ckevt_tcc88xx_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_tcc88xx_osmr0);
ckevt_tcc88xx_osmr0.min_delta_ns =
clockevent_delta2ns(4, &ckevt_tcc88xx_osmr0) + 1;
ckevt_tcc88xx_osmr0.cpumask = cpumask_of(0);
cksrc_tcc88xx_oscr.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_tcc88xx_oscr.shift);
BITSET(pPIC->SEL0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->IEN0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->INTMSK0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->MODEA0, TCC_ENABLE_BIT(INT_TC32));
setup_irq(INT_TC32, &tcc88xx_timer_irq);
clocksource_register(&cksrc_tcc88xx_oscr);
clockevents_register_device(&ckevt_tcc88xx_osmr0);
/*
* Set scale and timer for sched_clock
*/
setup_sched_clock(CLOCK_TICK_RATE);
clock_valid = 1;
}
/*****************************************************************************
Function Name : tcc_composite_ext_interrupt_sel()
******************************************************************************/
void tcc_composite_ext_interrupt_sel(char ext_int_num, char ext_int_sel)
{
#if defined(CONFIG_MACH_TCC9300ST) || defined(CONFIG_MACH_TCC8800ST)
char shift_bit;
#if defined(CONFIG_MACH_TCC9300ST)
PGPIOINT pHwGPIOINT = (volatile PGPIOINT)tcc_p2v(HwEINTSEL_BASE);
#else
PGPIO pHwGPIOINT = (volatile PGPIO)tcc_p2v(HwGPIO_BASE);
#endif
PPIC pHwPIC = (volatile PPIC)tcc_p2v(HwVPIC_BASE);
#if defined(CONFIG_MACH_TCC8800ST)
if(ext_int_num >= 3)
pHwPIC->EI37SEL = (pHwPIC->EI37SEL | (0x01<<ext_int_num));
#endif
if(ext_int_num < 4)
{
shift_bit = 8*(ext_int_num-0);
BITCSET(pHwGPIOINT->EINTSEL0, 0x7F<<shift_bit, ext_int_sel<<shift_bit);
}
else if(ext_int_num < 8)
{
shift_bit = 8*(ext_int_num-4);
BITCSET(pHwGPIOINT->EINTSEL1, 0x7F<<shift_bit, ext_int_sel<<shift_bit);
}
else if(ext_int_num < 12)
{
shift_bit = 8*(ext_int_num-8);
BITCSET(pHwGPIOINT->EINTSEL2, 0x7F<<shift_bit, ext_int_sel<<shift_bit);
}
#if defined(CONFIG_MACH_TCC9300ST)
else
{
shift_bit = 8*(ext_int_num-12);
BITCSET(pHwGPIOINT->EINTSEL3, 0x7F<<shift_bit, ext_int_sel<<shift_bit);
}
#endif
#elif defined(CONFIG_MACH_TCC8920ST)
tcc_gpio_config_ext_intr(ext_int_num, ext_int_sel);
#endif
}
/*------------------------------------------------------------------
Gre2d_Grp_enable
graphic engine channel enable control
-------------------------------------------------------------------*/
void Gre2d_Grp_enable(G2D_EN grp_enalbe, unsigned char int_en)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
#if defined(CONFIG_ARCH_TCC892X)
BITCSET( pHwOVERLAYMIXER->OM_CTRL.nREG, (HwGE_GE_CTRL_EN|HwGE_GE_INT_EN), ((int_en<<16)|grp_enalbe));
#else
BITCSET( pHwOVERLAYMIXER->OM_CTRL, (HwGE_GE_CTRL_EN|HwGE_GE_INT_EN), ((int_en<<16)|grp_enalbe));
#endif
}