static u32 tdm_fsl_starlite_read(struct tdm_adapter *adap,
u16 **input_tdm_buffer)
{
struct tdm_priv *priv = tdm_get_adapdata(adap);
u8 phase_rx;
u32 buf_addr, buf_size;
/* point to where to start for the current phase data processing */
int bytes_in_fifo_per_frame =
ALIGN_SIZE(priv->cfg.num_ch * priv->cfg.ch_width, 8);
if (priv->tdm_active == 0) {
dev_warn(priv->device, "TDM is not ready");
return 0;
}
if (priv->phase_rx == 0)
phase_rx = NUM_OF_TDM_BUF - 1;
else
phase_rx = priv->phase_rx - 1;
buf_size = bytes_in_fifo_per_frame * priv->cfg.num_frames;
buf_addr = buf_size * phase_rx;
*input_tdm_buffer = (u16 *)(priv->tdm_input_data + buf_addr);
return buf_size;
}
static u32 tdm_fsl_starlite_get_write_buf(struct tdm_adapter *adap,
u16 **output_tdm_buffer)
{
struct tdm_priv *priv = tdm_get_adapdata(adap);
u32 tmp;
u8 phase_tx;
u32 buf_addr, buf_size;
/* point to where to start for the current phase data processing */
int bytes_in_fifo_per_frame =
ALIGN_SIZE(priv->cfg.num_ch * priv->cfg.ch_width, 8);
if (priv->tdm_active == 0) {
dev_warn(priv->device, "TDM is not ready");
return 0;
}
tmp = in_be32(&priv->dmac_regs->tcd[TDMTX_DMA_CH].tcd[0]);
tmp -= priv->dma_tx_tcd[0]->tcd[0];
priv->phase_tx = tmp / (bytes_in_fifo_per_frame * priv->cfg.num_frames);
if (priv->phase_tx == 0)
phase_tx = NUM_OF_TDM_BUF - 1;
else
phase_tx = priv->phase_tx - 1;
buf_size = bytes_in_fifo_per_frame * priv->cfg.num_frames;
buf_addr = buf_size * phase_tx;
*output_tdm_buffer = (u16 *)(priv->tdm_output_data + buf_addr);
return buf_size;
}
static int tdm_fsl_starlite_disable(struct tdm_adapter *adap)
{
struct tdm_priv *priv = tdm_get_adapdata(adap);
if (priv->tdm_active == 0) {
dev_warn(priv->device, "already Disabled");
return 0;
}
priv->tdm_active = 0;
return 0;
}
static u32 tdm_fsl_get_write_buf(struct tdm_adapter *adap,
u16 **output_tdm_buffer)
{
struct tdm_priv *priv;
u32 tmp;
u32 phase_tx;
u32 buf_addr, buf_size;
int bytes_in_fifo_per_frame;
if (!adap) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
/* point to where to start for the current phase data processing */
bytes_in_fifo_per_frame =
ALIGN_SIZE(adap->adapt_cfg.num_ch * adap->adapt_cfg.slot_width, 8);
priv = tdm_get_adapdata(adap);
if (!priv) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
if (priv->tdm_active == 0) {
dev_warn(priv->device, "TDM is not ready");
return 0;
}
tmp = in_be32(&priv->dmac_regs->tcd[TDMTX_DMA_CH].tcd[0]);
tmp -= priv->dma_tx_tcd[0]->tcd[0];
priv->phase_tx = tmp/(bytes_in_fifo_per_frame *
adap->adapt_cfg.num_frames);
if (priv->phase_tx == 0)
phase_tx = NUM_OF_TDM_BUF - 1;
else
phase_tx = priv->phase_tx - 1;
buf_size = bytes_in_fifo_per_frame * adap->adapt_cfg.num_frames;
buf_addr = buf_size * phase_tx;
*output_tdm_buffer = (u16 *)(priv->tdm_output_data + buf_addr);
return buf_size;
}
static int tdm_fsl_disable(struct tdm_adapter *adap)
{
struct tdm_priv *priv;
if (!adap) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
priv = tdm_get_adapdata(adap);
if (priv->tdm_active == 0) {
dev_warn(priv->device, "already Disabled");
return 0;
}
priv->tdm_active = 0;
return 0;
}
static u32 tdm_fsl_read(struct tdm_adapter *adap,
u16 **input_tdm_buffer)
{
struct tdm_priv *priv;
u32 phase_rx;
u32 buf_addr, buf_size;
int bytes_in_fifo_per_frame;
if (!adap) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
/* point to where to start for the current phase data processing */
bytes_in_fifo_per_frame =
ALIGN_SIZE(adap->adapt_cfg.num_ch * adap->adapt_cfg.slot_width, 8);
priv = tdm_get_adapdata(adap);
if (!priv) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
if (priv->tdm_active == 0) {
dev_warn(priv->device, "TDM is not ready");
return 0;
}
if (priv->phase_rx == 0)
phase_rx = NUM_OF_TDM_BUF - 1;
else
phase_rx = priv->phase_rx - 1;
buf_size = bytes_in_fifo_per_frame * adap->adapt_cfg.num_frames;
buf_addr = buf_size * phase_rx;
*input_tdm_buffer = (u16 *)(priv->tdm_input_data + buf_addr);
return buf_size;
}
static int tdm_fsl_starlite_enable(struct tdm_adapter *adap)
{
int i;
u32 ch_enab[4];
unsigned long timeout;
struct tdm_priv *priv = tdm_get_adapdata(adap);
u8 ph = priv->phase_tx;
if (priv->tdm_active == 1) {
dev_warn(priv->device, "already Enabled");
return 0;
}
/* enable the Channels required 0 to number of ch -1 */
for (i = 0; i < 4; i++)
ch_enab[i] = 0;
for (i = 0; i < priv->cfg.num_ch; i++)
ch_enab[i / 32] |= (1 << (i & 0x1F));
for (i = 0; i < 4; i++) {
out_be32(&priv->tdm_regs->rcen[i], ch_enab[i]);
out_be32(&priv->tdm_regs->tcen[i], ch_enab[i]);
}
/* Clear the DONE bit */
out_8(&priv->dmac_regs->dmacdne, TDMRX_DMA_CH);
out_8(&priv->dmac_regs->dmacdne, TDMTX_DMA_CH);
/* Load the Tx transfer control descriptors */
for (i = 0; i < DMA_MAX_TCD; i++)
out_be32(&priv->dmac_regs->tcd[TDMTX_DMA_CH].tcd[i],
priv->dma_tx_tcd[ph]->tcd[i]);
/* Load the Rx transfer control descriptors */
for (i = 0; i < DMA_MAX_TCD; i++)
out_be32(&priv->dmac_regs->tcd[TDMRX_DMA_CH].tcd[i],
priv->dma_rx_tcd[ph]->tcd[i]);
/* enable the dma request */
out_8(&priv->dmac_regs->dmaserq, TDMRX_DMA_CH);
out_8(&priv->dmac_regs->dmaserq, TDMTX_DMA_CH);
/* Enable Receiver, transmitter */
timeout = jiffies + TDM_ENABLE_TIMEOUT;
out_be32(&priv->tdm_regs->tcr, TCR_TEN);
while (!(in_be32(&priv->tdm_regs->tsr) & TSR_TENS)) {
if (time_after(jiffies, timeout)) {
dev_err(priv->device, "timeout to enable TDM Tx\n");
return -ETIMEDOUT;
}
cpu_relax();
}
timeout = jiffies + TDM_ENABLE_TIMEOUT;
out_be32(&priv->tdm_regs->rcr, RCR_REN);
while (!(in_be32(&priv->tdm_regs->rsr) & RSR_RENS)) {
if (time_after(jiffies, timeout)) {
dev_err(priv->device, "timeout to enable TDM Rx\n");
return -ETIMEDOUT;
}
cpu_relax();
}
priv->tdm_active = 1;
return 1;
}
