static int tegra_max98088_set_dam_cif(int dam_ifc, int srate, int channels, int bit_size, int src_on, int src_srate, int src_channels, int src_bit_size) { tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN1, 0x1000); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHOUT, srate); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1, srate); tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1, channels, bit_size, channels, bit_size); tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT, channels, bit_size, channels, bit_size); if (src_on) { tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC, src_srate); tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC, src_channels, src_bit_size, 1, 16); } return 0; }
static int tegra_aic326x_set_dam_cif(int dam_ifc, int srate, int channels, int bit_size, int src_on, int src_srate, int src_channels, int src_bit_size) { tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN1, 0x1000); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHOUT, srate); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1, srate); #ifndef CONFIG_ARCH_TEGRA_3x_SOC tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1, channels, bit_size, channels, 32); tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT, channels, bit_size, channels, 32); #else tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1, channels, bit_size, channels, bit_size); tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT, channels, bit_size, channels, bit_size); #endif if (src_on) { tegra30_dam_set_gain(dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000); tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN0_SRC, src_srate); #ifndef CONFIG_ARCH_TEGRA_3x_SOC tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC, src_channels, src_bit_size, 1, 32); #else tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN0_SRC, src_channels, src_bit_size, 1, 16); #endif } return 0; }
static int tegra_max98095_startup(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai); if ((substream->stream != SNDRV_PCM_STREAM_PLAYBACK) || !(i2s->is_dam_used)) return 0; /*dam configuration*/ if (!i2s->dam_ch_refcount) i2s->dam_ifc = tegra30_dam_allocate_controller(); tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1); i2s->dam_ch_refcount++; tegra30_dam_enable_clock(i2s->dam_ifc); tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN1, 0x1000); tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 + (i2s->dam_ifc*2), i2s->txcif); /* *make the dam tx to i2s rx connection if this is the only client *using i2s for playback */ if (i2s->playback_ref_count == 1) tegra30_ahub_set_rx_cif_source( TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id, TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc); /* enable the dam*/ tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE, TEGRA30_DAM_CHIN1); return 0; }