void __init tegra_super_clk_gen4_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *params) { struct clk *clk; struct clk **dt_clk; /* CCLKG */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks); if (dt_clk) { clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, 0, 4, 0, 0, NULL); *dt_clk = clk; } /* CCLKLP */ dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks); if (dt_clk) { clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, ARRAY_SIZE(cclk_lp_parents), CLK_SET_RATE_PARENT, clk_base + CCLKLP_BURST_POLICY, TEGRA_DIVIDER_2, 4, 8, 9, NULL); *dt_clk = clk; } tegra_sclk_init(clk_base, tegra_clks); #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) /* PLLX */ dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks); if (!dt_clk) return; clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, pmc_base, CLK_IGNORE_UNUSED, params, NULL); *dt_clk = clk; /* PLLX_OUT0 */ dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks); if (!dt_clk) return; clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", CLK_SET_RATE_PARENT, 1, 2); *dt_clk = clk; #endif }
static void __init tegra132_ccplex(struct device_node *np) { struct clk *clk; struct device_node *node; clk_base = of_iomap(np, 0); if (!clk_base) { pr_err("ioremap tegra132 CCPLEX clk failed\n"); return; } node = of_find_matching_node(NULL, pmc_match); if (!node) { pr_err("Failed to find pmc node\n"); WARN_ON(1); return; } pmc_base = of_iomap(node, 0); if (!pmc_base) { pr_err("Can't map pmc registers\n"); WARN_ON(1); return; } clk = clk_register_mux(NULL, "cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, clk_base + CCLK_BURST_POLICY, 28, 4, 0, NULL); clks[TEGRA132_CCPLEX_CCLK_G] = clk; clk_register_clkdev(clk, "cclk_g", NULL); clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, pmc_base, CLK_IGNORE_UNUSED, &pll_x_params, NULL); clks[TEGRA132_PLL_X] = clk; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); tegra132_clock_apply_init_table(); #ifdef CONFIG_PM_SLEEP register_syscore_ops(&tegra_clk_syscore_ops); #endif }