void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor) { const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg; tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL, NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK, NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, NV_SOR_PLL3, NV_SOR_PLL3_PLLVDD_MODE_MASK, NV_SOR_PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, NV_SOR_PLL0, 0xf << NV_SOR_PLL0_ICHPMP_SHFIT | 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT | NV_SOR_PLL0_PLLREG_LEVEL_V45 | NV_SOR_PLL0_RESISTORSEL_EXT | NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, NV_SOR_PLL1, NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { printk(BIOS_ERR, "DP failed to lock PLL\n"); return; } tegra_sor_write_field(sor, NV_SOR_PLL2, NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE); tegra_dc_sor_power_up(sor, 0); /* re-enable SOR clock */ tegra_sor_enable_edp_clock(sor); // select pll_dp as clock source /* Power up lanes */ tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(sor, link_cfg); }
int tegra_dc_sor_enable_dp(struct udevice *dev, const struct tegra_dp_link_config *link_cfg) { struct tegra_dc_sor_data *sor = dev_get_priv(dev); int ret; tegra_sor_write_field(sor, CLK_CNTRL, CLK_CNTRL_DP_CLK_SEL_MASK, CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); tegra_sor_write_field(sor, PLL2, PLL2_AUX6_BANDGAP_POWERDOWN_MASK, PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); udelay(25); tegra_sor_write_field(sor, PLL3, PLL3_PLLVDD_MODE_MASK, PLL3_PLLVDD_MODE_V3_3); tegra_sor_writel(sor, PLL0, 0xf << PLL0_ICHPMP_SHFIT | 0x3 << PLL0_VCOCAP_SHIFT | PLL0_PLLREG_LEVEL_V45 | PLL0_RESISTORSEL_EXT | PLL0_PWR_ON | PLL0_VCOPD_RESCIND); tegra_sor_write_field(sor, PLL2, PLL2_AUX1_SEQ_MASK | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | PLL2_AUX9_LVDSEN_OVERRIDE | PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | PLL1_TMDS_TERM_ENABLE); if (tegra_dc_sor_poll_register(sor, PLL2, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 100, TEGRA_SOR_TIMEOUT_MS)) { printf("DP failed to lock PLL\n"); return -EIO; } tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | PLL2_AUX7_PORT_POWERDOWN_MASK, PLL2_AUX2_OVERRIDE_POWERDOWN | PLL2_AUX7_PORT_POWERDOWN_DISABLE); ret = tegra_dc_sor_power_up(dev, 0); if (ret) { debug("DP failed to power up\n"); return ret; } /* re-enable SOR clock */ clock_sor_enable_edp_clock(); /* Power up lanes */ tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1); tegra_dc_sor_set_dp_mode(dev, link_cfg); debug("%s ret\n", __func__); return 0; }