static void pluto_panel_select(void) { struct tegra_panel *panel; struct board_info board; u8 dsi_instance = 0; tegra_get_display_board_info(&board); switch (board.board_id) { case BOARD_E1605: panel = &dsi_j_720p_4_7; dsi_instance = DSI_INSTANCE_1; break; case BOARD_E1577: panel = &dsi_s_1080p_5; break; case BOARD_E1582: default: if (tegra_get_board_panel_id()) { panel = &dsi_s_1080p_5; dsi_instance = DSI_INSTANCE_1; } else { panel = &dsi_l_720p_5; dsi_instance = DSI_INSTANCE_0; } break; } if (panel->init_sd_settings) panel->init_sd_settings(&sd_settings); if (panel->init_dc_out) { panel->init_dc_out(&pluto_disp1_out); pluto_disp1_out.dsi->dsi_instance = dsi_instance; pluto_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; pluto_disp1_out.dsi->dsi_panel_bl_en_gpio = DSI_PANEL_BL_EN_GPIO; pluto_disp1_out.dsi->dsi_panel_bl_pwm_gpio = DSI_PANEL_BL_PWM_GPIO; /* update the init cmd if dependent on reset GPIO */ tegra_dsi_update_init_cmd_gpio_rst(&pluto_disp1_out); } if (panel->init_fb_data) panel->init_fb_data(&pluto_disp1_fb_data); if (panel->init_cmu_data) panel->init_cmu_data(&pluto_disp1_pdata); if (panel->set_disp_device) panel->set_disp_device(&pluto_disp1_device); tegra_dsi_resources_init(dsi_instance, pluto_disp1_resources, ARRAY_SIZE(pluto_disp1_resources)); if (panel->register_bl_dev) panel->register_bl_dev(); }
static void ceres_panel_select(void) { struct tegra_panel *panel; u8 dsi_instance = 0; //Ivan //panel = &dsi_otm1283a_720p; if (tegra_get_board_panel_id()==11) { //LIUJ201140504RELE1315ADDO adc select lcd panel = &dsi_hx8394a_720p; panel_name = "Tcl_hx8394_HD_video_24bit\n"; } else if (tegra_get_board_panel_id()==1) { panel = &dsi_s_1080p_5; panel_name = "Sharp_s_1080p_HD_video_24bit\n"; } else { panel = &dsi_otm1283a_720p; panel_name = "Truly_otm1283a_HD_video_24bit\n"; } dsi_instance = DSI_INSTANCE_0; if (panel->init_sd_settings) panel->init_sd_settings(&sd_settings); if (panel->init_dc_out) { panel->init_dc_out(&ceres_disp1_out); ceres_disp1_out.dsi->dsi_instance = dsi_instance; ceres_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; ceres_disp1_out.dsi->dsi_panel_bl_en_gpio = DSI_PANEL_BL_EN_GPIO; ceres_disp1_out.dsi->dsi_panel_bl_pwm_gpio = NULL; // DSI_PANEL_BL_PWM_GPIO; ceres_disp1_out.dsi->te_gpio = TE_GPIO; /* update the init cmd if dependent on reset GPIO */ tegra_dsi_update_init_cmd_gpio_rst(&ceres_disp1_out); } if (panel->init_fb_data) panel->init_fb_data(&ceres_disp1_fb_data); if (panel->init_cmu_data) panel->init_cmu_data(&ceres_disp1_pdata); if (panel->set_disp_device) panel->set_disp_device(&ceres_disp1_device); tegra_dsi_resources_init(dsi_instance, ceres_disp1_resources, ARRAY_SIZE(ceres_disp1_resources)); if (panel->register_bl_dev) panel->register_bl_dev(); }
static void macallan_panel_select(void) { struct tegra_panel *panel = NULL; struct board_info board; u8 dsi_instance = DSI_INSTANCE_0; tegra_get_display_board_info(&board); switch (board.board_id) { case BOARD_E1639: panel = &dsi_s_wqxga_10_1; break; default: panel = &dsi_p_wuxga_10_1; break; } if (panel) { if (panel->init_sd_settings) panel->init_sd_settings(&sd_settings); if (panel->init_dc_out) { panel->init_dc_out(&macallan_disp1_out); macallan_disp1_out.dsi->dsi_instance = dsi_instance; macallan_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; macallan_disp1_out.dsi->dsi_panel_bl_pwm_gpio = DSI_PANEL_BL_PWM_GPIO; } if (panel->init_fb_data) panel->init_fb_data(&macallan_disp1_fb_data); if (panel->init_cmu_data) panel->init_cmu_data(&macallan_disp1_pdata); if (panel->set_disp_device) panel->set_disp_device(&macallan_disp1_device); tegra_dsi_resources_init(dsi_instance, macallan_disp1_resources, ARRAY_SIZE(macallan_disp1_resources)); if (panel->register_bl_dev) panel->register_bl_dev(); if (panel->register_i2c_bridge) panel->register_i2c_bridge(); } }
static void pismo_panel_select(void) { struct tegra_panel *panel = NULL; panel = &dsi_a_1080p_11_6; if (panel) { if (panel->init_sd_settings) panel->init_sd_settings(&pismo_sd_settings); if (panel->init_dc_out) { panel->init_dc_out(&pismo_disp1_out); pismo_disp1_out.dsi->dsi_instance = DSI_INSTANCE_0; pismo_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; pismo_disp1_out.dsi->dsi_panel_bl_pwm_gpio = DSI_PANEL_BL_PWM_GPIO; } if (panel->init_fb_data) panel->init_fb_data(&pismo_disp1_fb_data); if (panel->init_cmu_data) panel->init_cmu_data(&pismo_disp1_pdata); if (panel->set_disp_device) panel->set_disp_device(&pismo_disp1_device); tegra_dsi_resources_init(pismo_disp1_out.dsi->dsi_instance, pismo_disp1_resources, ARRAY_SIZE(pismo_disp1_resources)); if (panel->register_bl_dev) panel->register_bl_dev(); if (panel->register_i2c_bridge) panel->register_i2c_bridge(); } }
static void ardbeg_panel_select(void) { struct tegra_panel *panel = NULL; struct board_info board; struct board_info mainboard; u8 dsi_instance; panel = ardbeg_panel_configure(&board, &dsi_instance); if (panel) { if (panel->init_sd_settings) panel->init_sd_settings(&sd_settings); if (panel->init_dc_out) { panel->init_dc_out(&ardbeg_disp1_out); if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) { ardbeg_disp1_out.dsi->dsi_instance = dsi_instance; ardbeg_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio = DSI_PANEL_BL_PWM_GPIO; ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6; } tegra_get_board_info(&mainboard); if ((mainboard.board_id == BOARD_E1784) || (mainboard.board_id == BOARD_P1761)) { ardbeg_disp1_out.rotation = 180; if ((board.board_id == BOARD_E1937) && (board.sku == 1000)) ardbeg_disp1_out.dsi-> dsi_panel_rst_gpio = TEGRA_GPIO_PN4; } } if (panel->init_fb_data) panel->init_fb_data(&ardbeg_disp1_fb_data); if (panel->init_cmu_data) panel->init_cmu_data(&ardbeg_disp1_pdata); if (panel->set_disp_device) panel->set_disp_device(&ardbeg_disp1_device); if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) { tegra_dsi_resources_init(dsi_instance, ardbeg_disp1_resources, ARRAY_SIZE(ardbeg_disp1_resources)); } if (panel->register_bl_dev) panel->register_bl_dev(); if (panel->register_i2c_bridge) panel->register_i2c_bridge(); } }