static void unpowergate(struct nvhost_module *mod)
{
const struct nvhost_moduledesc *desc = mod->desc;
if (desc->can_powergate) {
if (desc->powergate_ids[0] != -1)
tegra_unpowergate_partition(desc->powergate_ids[0]);
if (desc->powergate_ids[1] != -1)
tegra_unpowergate_partition(desc->powergate_ids[1]);
}
}
static int tegra_camera_power_on(struct tegra_camera_dev *dev)
{
int ret = 0;
dev_dbg(dev->dev, "%s++\n", __func__);
/* Enable external power */
if (dev->reg) {
ret = regulator_enable(dev->reg);
if (ret) {
dev_err(dev->dev,
"%s: enable csi regulator failed.\n",
__func__);
return ret;
}
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Unpowergate VE */
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
if (ret)
dev_err(dev->dev,
"%s: unpowergate failed.\n",
__func__);
#endif
dev->power_on = 1;
tegra_camera_on = dev->power_on;
return ret;
}
static int tegra_camera_power_on(struct tegra_camera_dev *dev)
{
int ret = 0;
if (dev->power_refcnt++ == 0) {
#if !defined(CONFIG_MACH_PICASSO_E)
/* Enable external power */
if (dev->reg) {
ret = regulator_enable(dev->reg);
if (ret) {
dev_err(dev->dev,
"%s: enable csi regulator failed.\n",
__func__);
return ret;
}
}
#endif
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Unpowergate VE */
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
if (ret)
dev_err(dev->dev,
"%s: unpowergate failed.\n",
__func__);
#endif
}
return ret;
}
int nvhost_module_init(struct nvhost_module *mod, const char *name,
const struct nvhost_moduledesc *desc,
struct nvhost_module *parent,
struct device *dev)
{
int i = 0;
mod->name = name;
INIT_LIST_HEAD(&mod->client_list);
while (desc->clocks[i].name && i < NVHOST_MODULE_MAX_CLOCKS) {
char devname[MAX_DEVID_LENGTH];
long rate = desc->clocks[i].default_rate;
snprintf(devname, MAX_DEVID_LENGTH, "tegra_%s", name);
mod->clk[i] = clk_get_sys(devname, desc->clocks[i].name);
BUG_ON(IS_ERR_OR_NULL(mod->clk[i]));
rate = clk_round_rate(mod->clk[i], rate);
clk_enable(mod->clk[i]);
clk_set_rate(mod->clk[i], rate);
clk_disable(mod->clk[i]);
i++;
}
mod->num_clks = i;
mod->desc = desc;
mod->parent = parent;
mod->powered = false;
mutex_init(&mod->lock);
init_waitqueue_head(&mod->idle);
INIT_DELAYED_WORK(&mod->powerdown, powerdown_handler);
if (!desc->can_powergate) {
if (desc->powergate_ids[0] != -1)
tegra_unpowergate_partition(desc->powergate_ids[0]);
if (desc->powergate_ids[1] != -1)
tegra_unpowergate_partition(desc->powergate_ids[1]);
}
if (desc->init)
desc->init(dev, mod);
return 0;
}
int tegra_camera_power_on(struct tegra_camera *camera)
{
int ret = 0;
dev_dbg(camera->dev, "%s++\n", __func__);
/* Enable external power */
if (camera->reg) {
ret = regulator_enable(camera->reg);
if (ret) {
dev_err(camera->dev,
"%s: enable csi regulator failed.\n",
__func__);
return ret;
}
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Powergating DIS must powergate VE partition. Camera
* module needs to increase the ref-count of disa to
* avoid itself powergated by DIS inadvertently. */
#ifndef CONFIG_ARCH_TEGRA_3x_SOC
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_DISA);
if (ret)
dev_err(camera->dev,
"%s: DIS unpowergate failed.\n",
__func__);
#endif
/* Unpowergate VE */
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
if (ret)
dev_err(camera->dev,
"%s: VENC unpowergate failed.\n",
__func__);
#endif
camera->power_on = 1;
return ret;
}
int tegraxx_unpowergate_partition_with_clk_on(int id,
struct powergate_partition_info *pg_info)
{
int ret = 0;
ret = tegra_unpowergate_partition(id);
if (ret)
goto err_unpowergating;
/* Enable clks for the partition */
ret = partition_clk_enable(pg_info);
if (ret)
goto err_unpowergate_clk;
return ret;
err_unpowergate_clk:
tegra_powergate_partition(id);
WARN(1, "Could not Un-Powergate %d, err in enabling clk", id);
err_unpowergating:
WARN(1, "Could not Un-Powergate %d", id);
return ret;
}
static long tegra_camera_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
uint id;
/* first element of arg must be u32 with id of module to talk to */
if (copy_from_user(&id, (const void __user *)arg, sizeof(uint))) {
pr_err("%s: Failed to copy arg from user", __func__);
return -EFAULT;
}
if (id >= ARRAY_SIZE(tegra_camera_block)) {
pr_err("%s: Invalid id to tegra isp ioctl%d\n", __func__, id);
return -EINVAL;
}
switch (cmd) {
case TEGRA_CAMERA_IOCTL_ENABLE:
{
int ret = 0;
mutex_lock(&tegra_camera_lock);
/* Unpowergate camera blocks (vi, csi and isp)
before enabling clocks */
if (tegra_camera_powergate++ == 0) {
ret = tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
if (ret) {
tegra_powergate_partition(TEGRA_POWERGATE_VENC);
pr_err("%s: Unpowergating failed.\n", __func__);
tegra_camera_powergate = 0;
mutex_unlock(&tegra_camera_lock);
return ret;
}
}
if (!tegra_camera_block[id].is_enabled) {
ret = tegra_camera_block[id].enable();
tegra_camera_block[id].is_enabled = true;
}
mutex_unlock(&tegra_camera_lock);
return ret;
}
case TEGRA_CAMERA_IOCTL_DISABLE:
{
int ret = 0;
mutex_lock(&tegra_camera_lock);
if (tegra_camera_block[id].is_enabled) {
ret = tegra_camera_block[id].disable();
tegra_camera_block[id].is_enabled = false;
}
/* Powergate camera blocks (vi, csi and isp)
after disabling all the clocks */
if (!ret) {
if (--tegra_camera_powergate == 0) {
ret = tegra_powergate_partition(TEGRA_POWERGATE_VENC);
if (ret)
pr_err("%s: Powergating failed.\n", __func__);
}
}
mutex_unlock(&tegra_camera_lock);
return ret;
}
case TEGRA_CAMERA_IOCTL_CLK_SET_RATE:
{
struct tegra_camera_clk_info info;
int ret;
if (copy_from_user(&info, (const void __user *)arg,
sizeof(struct tegra_camera_clk_info))) {
pr_err("%s: Failed to copy arg from user\n", __func__);
return -EFAULT;
}
ret = tegra_camera_clk_set_rate(&info);
if (ret)
return ret;
if (copy_to_user((void __user *)arg, &info,
sizeof(struct tegra_camera_clk_info))) {
pr_err("%s: Failed to copy arg to user\n", __func__);
return -EFAULT;
}
return 0;
}
case TEGRA_CAMERA_IOCTL_RESET:
return tegra_camera_reset(id);
default:
pr_err("%s: Unknown tegra_camera ioctl.\n", TEGRA_CAMERA_NAME);
return -EINVAL;
}
return 0;
}
static int power_up_cpu(unsigned int cpu)
{
u32 reg;
int ret = 0;
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
unsigned long timeout;
BUG_ON(cpu == smp_processor_id());
BUG_ON(is_lp_cluster());
/* If this cpu has booted this function is entered after
* CPU has been already un-gated by flow controller. Wait
* for confirmation that cpu is powered and remove clamps.
* On first boot entry do not wait - go to direct ungate.
*/
if (cpu_isset(cpu, tegra_cpu_init_map)) {
timeout = jiffies + 5;
do {
if (is_cpu_powered(cpu))
goto remove_clamps;
udelay(10);
} while (time_before(jiffies, timeout));
}
/* First boot or Flow controller did not work as expected. Try to
directly toggle power gates. Error if direct power on also fails. */
if (!is_cpu_powered(cpu)) {
ret = tegra_unpowergate_partition(TEGRA_CPU_POWERGATE_ID(cpu));
if (ret)
goto fail;
/* Wait for the power to come up. */
timeout = jiffies + 10*HZ;
do {
if (is_cpu_powered(cpu))
goto remove_clamps;
udelay(10);
} while (time_before(jiffies, timeout));
ret = -ETIMEDOUT;
goto fail;
}
remove_clamps:
/* CPU partition is powered. Enable the CPU clock. */
writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
udelay(10);
/* Remove I/O clamps. */
ret = tegra_powergate_remove_clamping(TEGRA_CPU_POWERGATE_ID(cpu));
udelay(10);
fail:
#else
/* Enable the CPU clock. */
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
barrier();
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
#endif
/* Clear flow controller CSR. */
flowctrl_writel(0, FLOW_CTRL_CPU_CSR(cpu));
return ret;
}
