static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. */
timer_set_prescaler(TIM2, 36000);
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
void PPMin_TIM_Init()
{
/* Enable TIM1 clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* No Enable TIM1 interrupt. */
// nvic_enable_irq(NVIC_TIM1_IRQ);
// nvic_set_priority(NVIC_TIM1_IRQ, 16); //High priority
/* Reset TIM1 peripheral. */
timer_disable_counter(TIM1);
timer_reset(TIM1);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. timer updates each uSecond */
timer_set_prescaler(TIM1, PPMIn_prescaler); // uSecond (72MHz / (35+1) = 2MHz = 0.5uSecond
timer_set_period(TIM1, PPMIn_period); // 3300uSecond= 2MHz*6600times, TIM1_prescaler=0.5uSecond
/* Disable preload. */
timer_disable_preload(TIM1);
/* Continous mode. */
timer_continuous_mode(TIM1);
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
/* Enable CCP1 */
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_disable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
/* Enable commutation interrupt. */
// timer_enable_irq(TIM1, TIM_DIER_CC1IE);
/* Disable CCP1 interrupt. */
timer_disable_irq(TIM1, TIM_DIER_CC1IE);
/* Counter enable. */
timer_disable_counter(TIM1);
}
void sound_set_frequency(uint32_t freq) {
uint32_t prescaler, period;
if (freq <= 200) {
// switch off pwm
timer_disable_oc_output(TIM1, TIM_OC1);
// return;
}
// reset TIMx peripheral
timer_reset(TIM1);
// roughly factor into 16-bit
period = (rcc_timer_frequency / 1) / freq;
prescaler = (period / 65536) + 1;
period = (period / prescaler);
// Set the timers global mode to:
// - use no divider
// - alignment edge
// - count direction up
timer_set_mode(TIM1,
TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE,
TIM_CR1_DIR_UP);
timer_set_prescaler(TIM1, prescaler - 1);
timer_set_repetition_counter(TIM1, 0);
timer_enable_preload(TIM1);
timer_continuous_mode(TIM1);
timer_set_period(TIM1, period - 1);
// start with disabled pwm output
timer_disable_oc_output(TIM1, TIM_OC1);
// NOTE: on advanced timers as TIM1 we have
// to break the main output, otherwise
// no pwm output signal will be present on pin
timer_enable_break_main_output(TIM1);
// configure output mode
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
// set period for 50/50 duty cycle
timer_set_oc_value(TIM1, TIM_OC1, period / 2);
// enable pwm output
timer_enable_oc_output(TIM1, TIM_OC1);
// start timer
timer_enable_counter(TIM1);
}
/******************************************************************************
Initializes the timer, turn on the interrupt and put the interrupt time to zero
INPUT void
OUTPUT void
The timer is set to roll over at 0.5 second from an 8us clock, and the output
compare 1 is used to trigger an alarm. This is set progressively by the
CanFestival stack.
******************************************************************************/
void initTimer(void)
{
/* Set alarm back to zero */
timerAlarm = 0;
/* Enable TIM3 clock. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
/* Enable TIM3 interrupt. */
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Set prescaler to give 8us clock */
timer_set_prescaler(TIM3, 576);
/* Set the period as 0.5 second */
timer_set_period(TIM3, TIMEVAL_MAX);
/* Disable physical pin outputs. */
timer_disable_oc_output(TIM3, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_FROZEN);
/* Set the initial compare value for OC1. */
timer_set_oc_value(TIM3, TIM_OC1, timerAlarm);
/* Continous counting mode. */
timer_continuous_mode(TIM3);
/* ARR reload disable. */
timer_disable_preload(TIM3);
/* Counter enable. */
timer_enable_counter(TIM3);
/* Enable compare match interrupt. */
timer_enable_irq(TIM3, TIM_DIER_CC1IE);
}
void enable_test_trigger(trigger_type trig, unsigned int rpm) {
if (trig != FORD_TFI) {
return;
}
timeval_t t = time_from_rpm_diff(rpm, 45);
/* Set up TIM5 as 32bit clock */
rcc_periph_clock_enable(RCC_TIM5);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0);
gpio_set_af(GPIOA, GPIO_AF2, GPIO0);
timer_reset(TIM5);
timer_disable_oc_output(TIM5, TIM_OC1);
timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM5, (unsigned int)t);
timer_set_prescaler(TIM5, 0);
timer_disable_preload(TIM5);
timer_continuous_mode(TIM5);
/* Setup output compare registers */
timer_ic_set_input(TIM5, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM5, TIM_OC1);
timer_disable_oc_preload(TIM5, TIM_OC1);
timer_set_oc_slow_mode(TIM5, TIM_OC1);
timer_set_oc_mode(TIM5, TIM_OC1, TIM_OCM_TOGGLE);
timer_set_oc_value(TIM5, TIM_OC1, t);
timer_set_oc_polarity_high(TIM5, TIM_OC1);
timer_enable_oc_output(TIM5, TIM_OC1);
timer_enable_counter(TIM5);
}
static void pwm_setup(void) {
/* Configure GPIOs: OUT=PA7 */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM3_CH2 );
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_oc_output(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_enable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_set_dma_on_update_event(TIM3);
timer_enable_irq(TIM3, TIM_DIER_UDE); // in fact, enable DMA on update
timer_enable_preload(TIM3);
timer_continuous_mode(TIM3);
timer_set_period(TIM3, WSP);
timer_enable_counter(TIM3);
}
static void platform_init_eventtimer() {
/* Set up TIM2 as 32bit clock */
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM2, 0xFFFFFFFF);
timer_set_prescaler(TIM2, 0);
timer_disable_preload(TIM2);
timer_continuous_mode(TIM2);
/* Setup output compare registers */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Setup input captures for CH2-4 Triggers */
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3);
gpio_set_af(GPIOB, GPIO_AF1, GPIO3);
timer_ic_set_input(TIM2, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_filter(TIM2, TIM_IC2, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC2, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC2);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10);
gpio_set_af(GPIOB, GPIO_AF1, GPIO10);
timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI3);
timer_ic_set_filter(TIM2, TIM_IC3, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC3, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC3);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOB, GPIO_AF1, GPIO11);
timer_ic_set_input(TIM2, TIM_IC4, TIM_IC_IN_TI4);
timer_ic_set_filter(TIM2, TIM_IC4, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC4, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC4);
timer_enable_counter(TIM2);
timer_enable_irq(TIM2, TIM_DIER_CC2IE);
timer_enable_irq(TIM2, TIM_DIER_CC3IE);
timer_enable_irq(TIM2, TIM_DIER_CC4IE);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 0);
}
static void platform_init_pwm() {
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO7);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9);
gpio_set_af(GPIOC, GPIO_AF2, GPIO6);
gpio_set_af(GPIOC, GPIO_AF2, GPIO7);
gpio_set_af(GPIOC, GPIO_AF2, GPIO8);
gpio_set_af(GPIOC, GPIO_AF2, GPIO9);
timer_reset(TIM3);
timer_disable_oc_output(TIM3, TIM_OC1);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 72ish Hz, close to 60 */
timer_set_period(TIM3, 65535);
timer_set_prescaler(TIM3, 16);
timer_disable_preload(TIM3);
timer_continuous_mode(TIM3);
/* Setup output compare registers */
timer_ic_set_input(TIM3, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC1, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC1);
timer_enable_oc_output(TIM3, TIM_OC1);
timer_ic_set_input(TIM3, TIM_IC2, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_disable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_slow_mode(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_ic_set_input(TIM3, TIM_IC3, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC3);
timer_disable_oc_preload(TIM3, TIM_OC3);
timer_set_oc_slow_mode(TIM3, TIM_OC3);
timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC3, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC3);
timer_enable_oc_output(TIM3, TIM_OC3);
timer_ic_set_input(TIM3, TIM_IC4, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC4);
timer_disable_oc_preload(TIM3, TIM_OC4);
timer_set_oc_slow_mode(TIM3, TIM_OC4);
timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC4, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC4);
timer_enable_oc_output(TIM3, TIM_OC4);
timer_enable_counter(TIM3);
}
/** Set PWM channel configuration
*/
static inline void actuators_pwm_arch_channel_init(uint32_t timer_peripheral,
enum tim_oc_id oc_id) {
timer_disable_oc_output(timer_peripheral, oc_id);
timer_disable_oc_clear(timer_peripheral, oc_id);
timer_enable_oc_preload(timer_peripheral, oc_id);
timer_set_oc_slow_mode(timer_peripheral, oc_id);
timer_set_oc_mode(timer_peripheral, oc_id, TIM_OCM_PWM1);
timer_set_oc_polarity_high(timer_peripheral, oc_id);
timer_enable_oc_output(timer_peripheral, oc_id);
}
static void platform_init_freqsensor(unsigned char pin) {
uint32_t tim;
switch(pin) {
case 1:
/* TIM1 CH1 */
tim = TIM1;
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
gpio_set_af(GPIOA, GPIO_AF1, GPIO8);
break;
};
timer_reset(tim);
timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(tim, 0xFFFFFFFF);
timer_disable_preload(tim);
timer_continuous_mode(tim);
/* Setup output compare registers */
timer_disable_oc_output(tim, TIM_OC1);
timer_disable_oc_output(tim, TIM_OC2);
timer_disable_oc_output(tim, TIM_OC3);
timer_disable_oc_output(tim, TIM_OC4);
/* Set up compare */
timer_ic_set_input(tim, TIM_IC1, TIM_IC_IN_TI1);
timer_ic_set_filter(tim, TIM_IC1, TIM_IC_CK_INT_N_8);
timer_ic_set_polarity(tim, TIM_IC1, TIM_IC_RISING);
timer_set_prescaler(tim, 2*SENSOR_FREQ_DIVIDER); /* Prescale set to map up to 20kHz */
timer_slave_set_mode(tim, TIM_SMCR_SMS_RM);
timer_slave_set_trigger(tim, TIM_SMCR_TS_IT1FP1);
timer_ic_enable(tim, TIM_IC1);
timer_enable_counter(tim);
timer_enable_irq(tim, TIM_DIER_CC1IE);
switch(pin) {
case 1:
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
nvic_set_priority(NVIC_TIM1_CC_IRQ, 64);
break;
}
}
void tim3_isr(void)
{
if (timer_interrupt_source(TIM3,TIM_SR_UIF)) {
timer_clear_flag(TIM3,TIM_SR_UIF);
timer_set_oc_value(TIM3, TIM_OC1, PULSE);
timer_disable_oc_output(TIM3,TIM_OC2);
timer_disable_oc_output(TIM3,TIM_OC4);
//timer_disable_irq(TIM3,TIM_OC2);
//timer_disable_irq(TIM3,TIM_OC4);
timer_enable_irq(TIM3,TIM_DIER_CC1IE);
//gpio_set(GPIOA,GPIO1);
}
if ( timer_interrupt_source(TIM3,TIM_SR_CC1IF)) {
timer_clear_flag(TIM3,TIM_SR_CC1IF);
//if (PERIOD >= TIM3_CCR1) {
//gpio_clear(GPIOA,GPIO1);
timer_enable_oc_output(TIM3, TIM_OC2);
//timer_enable_irq(TIM3,TIM_DIER_CC2IE);
// }
}
if(timer_interrupt_source(TIM3,TIM_SR_CC2IF)) {
timer_clear_flag(TIM3,TIM_SR_CC2IF);
timer_set_oc_value(TIM3, TIM_OC1, PULSE*4);
//timer_enable_oc_output(TIM3,TIM_OC1);
timer_disable_oc_output(TIM3,TIM_OC2);
//timer_disable_irq(TIM3,TIM_DIER_CC2IE);
}
if(timer_interrupt_source(TIM3,TIM_SR_CC3IF)) {
timer_clear_flag(TIM3,TIM_SR_CC3IF);
timer_enable_oc_output(TIM3,TIM_OC4);
//timer_enable_irq(TIM3,TIM_DIER_CC4IE);
}
if(timer_interrupt_source(TIM3,TIM_SR_CC4IF)) {
//timer_disable_oc_output(TIM3,TIM_OC4);
}
}
void SVM_voltage_switch_inverter_VSI(float duty_A,float duty_B,float duty_C,bool shutdown)
{
//DTC-SVM switching selection
float Attenuation;
if (shutdown==false)
{
Attenuation=1.0f;
//-------------SA: S1 and S4------------------------------------
timer_set_oc_mode (TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_enable_oc_output (TIM1, TIM_OC1 ); //S1
timer_enable_oc_output (TIM1, TIM_OC1N); //S4}
//-------------SB: S3 and S6------------------------------------
timer_set_oc_mode (TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_enable_oc_output (TIM1, TIM_OC2 ); //S3
timer_enable_oc_output (TIM1, TIM_OC2N); //S6
//-------------SC: S5 and S2-------------------------------------
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_enable_oc_output (TIM1, TIM_OC3 ); //S5 on
timer_enable_oc_output (TIM1, TIM_OC3N); //S2 off
}
else
{
Attenuation=0.0f;
duty_A=0.0f;
duty_B=0.0f;
duty_C=0.0f;
//-------------SA: S1 and S4------------------------------------
timer_set_oc_mode (TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_disable_oc_output (TIM1, TIM_OC1 ); //S1
timer_disable_oc_output (TIM1, TIM_OC1N); //S4}
//-------------SB: S3 and S6------------------------------------
timer_set_oc_mode (TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_disable_oc_output (TIM1, TIM_OC2 ); //S3
timer_disable_oc_output (TIM1, TIM_OC2N); //S6
//-------------SC: S5 and S2-------------------------------------
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_disable_oc_output (TIM1, TIM_OC3 ); //S5 on
timer_disable_oc_output (TIM1, TIM_OC3N); //S2 off
}
//Set the capture compare value for OC1.
timer_set_oc_value(TIM1, TIM_OC1, duty_A*Attenuation*PWM_PERIOD_ARR);
//Set the capture compare value for OC1.
timer_set_oc_value(TIM1, TIM_OC2, duty_B*Attenuation*PWM_PERIOD_ARR);
//Set the capture compare value for OC1.
timer_set_oc_value(TIM1, TIM_OC3, duty_C*Attenuation*PWM_PERIOD_ARR);
}
/** Set PWM channel configuration
*/
void actuators_pwm_arch_channel_init(uint32_t timer_peripheral,
enum tim_oc_id oc_id) {
timer_disable_oc_output(timer_peripheral, oc_id);
//There is no such register in TIM9 and 12.
if (timer_peripheral != TIM9 && timer_peripheral != TIM12)
timer_disable_oc_clear(timer_peripheral, oc_id);
timer_enable_oc_preload(timer_peripheral, oc_id);
timer_set_oc_slow_mode(timer_peripheral, oc_id);
timer_set_oc_mode(timer_peripheral, oc_id, TIM_OCM_PWM1);
timer_set_oc_polarity_high(timer_peripheral, oc_id);
timer_enable_oc_output(timer_peripheral, oc_id);
// Used for TIM1 and TIM8, the function does nothing if other timer is specified.
timer_enable_break_main_output(timer_peripheral);
}
void PulseWidth::enable_output(uint8 channel)
{
if(timer_peripheral == TIM2)
{
if(channel >= 4)
return;
//rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
(1 << channel));
}
else if(timer_peripheral == TIM3)
{
switch(channel)
{
case 0:
case 1:
{
//rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
(1 << (channel+6)));
}
break;
case 2:
case 3:
{
//rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
(1 << (channel-2)));
}
break;
}
}
else
return;
tim_oc_id tid = static_cast<tim_oc_id>((channel%4)*2);
timer_disable_oc_output(timer_peripheral, tid);
timer_set_oc_mode(timer_peripheral, tid, TIM_OCM_PWM1);
timer_set_oc_value(timer_peripheral, tid, 0);
timer_enable_oc_output(timer_peripheral, tid);
}
void Beep(u16 frequency, u8 volume)
{
if (volume == 0) {
//We need to keep the timer running (for the vibration motor, but also in case there is a pause in the music)
//But don't want the buzzer running
timer_disable_oc_output(BEEP_TIM, BEEP_TIM_OC);
} else {
timer_enable_oc_output(BEEP_TIM, BEEP_TIM_OC);
}
/* volume is between 0 and 100 */
/* period = 14400000 / frequency */
/* A Period of 65535 gives a ~ 220Hz tone */
/* The Devo buzzer reaches max-volume with a pw ~ 100us. That is max volume */
/* use quadratic to approximate exponential volume control */
u32 period = 14400000 / frequency;
/* Taylor series: x + x^2/2 + x^3/6 + x^4/24 */
u32 duty_cycle = volume == 100 ? (period >> 1) : (u32)volume * volume * volume * 12 / 10000;
timer_set_period(BEEP_TIM, period);
timer_set_oc_value(BEEP_TIM, BEEP_TIM_OC, duty_cycle);
}
/*--------------------------------------------------------------------*/
void timer_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
timer_reset(TIM2);
/* Timer global mode: - No divider, Alignment edge, Direction up */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM2);
timer_set_period(TIM2, 1000);
timer_disable_oc_output(TIM2, TIM_OC2 | TIM_OC3 | TIM_OC4);
timer_enable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_TOGGLE);
timer_set_oc_value(TIM2, TIM_OC1, 500);
timer_disable_preload(TIM2);
/* Set the timer trigger output (for the DAC) to the channel 1 output compare */
timer_set_master_mode(TIM2, TIM_CR2_MMS_COMPARE_OC1REF);
timer_enable_counter(TIM2);
}
/**
* Commutation timer hardware initialization.
*/
void comm_tim_init(void)
{
comm_tim_data.freq = 65535;
(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));
/* TIM2 clock enable */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
/* Enable the TIM2 gloabal interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* TIM2 time base configuration */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE,
TIM_CR1_DIR_UP);
/* Set prescaler value */
timer_set_prescaler(TIM2, 4);
/* Disable preload. */
timer_disable_preload(TIM2);
/* Set continous mode. */
timer_continuous_mode(TIM2);
/* Set period to maximum */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* TIM2 Output Compare Timing Mode configuration: Channel1 */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
//timer_set_oc_polarity_high(TIM2, TIM_OC1);
/* Set initial capture compare value for OC1 */
timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq);
/* ARR reload enable */
timer_disable_preload(TIM2);
/* Counter enable */
timer_enable_counter(TIM2);
/* TIM2 Capture Compare 1 IT enable */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* TIM2 Update IT enable */
timer_enable_irq(TIM2, TIM_DIER_UIE);
comm_tim_reset();
}
static void timer_setup(void)
{
/* Enable TIM3 clock. */
rcc_periph_clock_enable(RCC_TIM3);
timer_reset(TIM3);
/* Timer global mode: - No divider, Alignment edge, Direction up */
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM3);
timer_set_period(TIM3, PERIOD);
timer_disable_preload(TIM3);
/* prescaler F_SYS/48 = TIM3 clock is 1 MHz */
timer_set_prescaler(TIM3,48);
//timer_disable_oc_output(TIM3, TIM_OC2 | TIM_OC3 | TIM_OC4);
timer_enable_oc_output(TIM3, TIM_OC1);
timer_disable_oc_output(TIM3,TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC3);
//timer_enable_oc_output(TIM3, TIM_OC4);
// motor ch1
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
// motor ch2
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
// motor ch3
timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
// motor ch3
timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
/* disable preload */
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC2);
timer_disable_oc_preload(TIM3, TIM_OC3);
timer_disable_oc_preload(TIM3, TIM_OC4);
/* polarity */
timer_set_oc_polarity_high(TIM3,TIM_OC1);
timer_set_oc_polarity_high(TIM3,TIM_OC2);
timer_set_oc_polarity_high(TIM3,TIM_OC3);
timer_set_oc_polarity_high(TIM3,TIM_OC4);
//timer_enable_oc_clear(TIM3, TIM_OC1);
//timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_value(TIM3, TIM_OC1, PULSE);
timer_set_oc_value(TIM3, TIM_OC2, PULSE*3);
timer_set_oc_value(TIM3, TIM_OC3, PULSE*2);
timer_set_oc_value(TIM3, TIM_OC4, PULSE*4);
//timer_generate_event(TIM3,TIM_EGR_CC1G);
//timer_enable_update_event(TIM3);
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_enable_irq(TIM3,TIM_DIER_CC1IE);
timer_enable_irq(TIM3,TIM_DIER_CC2IE);
timer_enable_irq(TIM3,TIM_DIER_CC3IE);
timer_enable_irq(TIM3,TIM_DIER_CC4IE);
//timer_enable_irq(TIM3,TIM_DIER_CC2IE);
timer_enable_irq(TIM3,TIM_DIER_UIE);
/* Set the timer trigger output (for the DAC) to the channel 1 output
compare */
//timer_set_master_mode(TIM3, TIM_CR2_MMS_COMPARE_OC1REF);
timer_enable_counter(TIM3);
}
static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value.
* Running the clock at 5kHz.
*/
/*
* On STM32F4 the timers are not running directly from pure APB1 or
* APB2 clock busses. The APB1 and APB2 clocks used for timers might
* be the double of the APB1 and APB2 clocks. This depends on the
* setting in DCKCFGR register. By default the behaviour is the
* following: If the Prescaler APBx is greater than 1 the derived timer
* APBx clocks will be double of the original APBx frequencies. Only if
* the APBx prescaler is set to 1 the derived timer APBx will equal the
* original APBx frequencies.
*
* In our case here the APB1 is devided by 4 system frequency and APB2
* divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will
* be 2 x APB2. So when we try to calculate the prescaler value we have
* to use rcc_apb1_freqency * 2!!!
*
* For additional information see reference manual for the stm32f4
* familiy of chips. Page 204 and 213
*/
timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
void motor_TIMER_config(void)
{
timer_period = rcc_ppre1_frequency / 5000;
timer_reset(TIM3);
/* set timer mode no divider ; alignment on edge ; direction up */
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM3);
/* Period (5kHz). TIM3 clk source is APB1*/
timer_set_period(TIM3, timer_period);
/* Reset prescaler value. */
timer_set_prescaler(TIM3, 0);
motor_front_left = 0;
motor_rear_left = 0;
motor_front_rigth = 0;
motor_rear_rigth = 0;
/************ channels configuration ************/
timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT);
timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT);
//configure OCx line
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_LEFT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_LEFT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_RIGHT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_RIGHT, TIM_OCM_PWM1);
//configure OCx output
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_RIGHT);
/* Set the capture compare value */
timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_LEFT, motor_front_left);
timer_set_oc_value(TIM3, MOTOR_PWM_REAR_LEFT, motor_rear_left);
timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_RIGHT, motor_front_rigth);
timer_set_oc_value(TIM3, MOTOR_PWM_REAR_RIGHT, motor_rear_rigth);
timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT);
timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_enable_counter(TIM3);
}
void PID_tim_init(void)
{
/* Enable TIM1 clock. and Port E clock (for outputs) */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
//Set TIM1 channel (and complementary) output to alternate function push-pull'.
//f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3
//f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N
gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13);
gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13);
gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12);
gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12);
/* Enable TIM1 commutation interrupt. */
//nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4
/* Reset TIM1 peripheral. */
timer_reset(TIM1);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now.
TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE
//TIM_CR1_CMS_CENTER_1
//TIM_CR1_CMS_CENTER_2
//TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal)
TIM_CR1_DIR_UP);
timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed)
timer_set_repetition_counter(TIM1, 0); //disabled
timer_enable_preload(TIM1);
timer_continuous_mode(TIM1);
/* Period (32kHz). */
timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter)
/* Configure break and deadtime. */
//timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR);
timer_set_enabled_off_state_in_idle_mode(TIM1);
timer_set_enabled_off_state_in_run_mode(TIM1);
timer_disable_break(TIM1);
timer_set_break_polarity_high(TIM1);
timer_disable_break_automatic_output(TIM1);
timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF);
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC1N);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC2N);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC3N);
/* -- OC1 and OC1N configuration -- */
/* Configure global mode of line 1. */
timer_enable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
/* Configure OC1. */
timer_set_oc_polarity_high(TIM1, TIM_OC1);
timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output
/* Configure OC1N. */
timer_set_oc_polarity_high(TIM1, TIM_OC1N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC1N);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);
/* -- OC2 and OC2N configuration -- */
/* Configure global mode of line 2. */
timer_enable_oc_preload(TIM1, TIM_OC2);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
/* Configure OC2. */
timer_set_oc_polarity_high(TIM1, TIM_OC2);
timer_set_oc_idle_state_unset(TIM1, TIM_OC2);
/* Configure OC2N. */
timer_set_oc_polarity_high(TIM1, TIM_OC2N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC2N);
/* Set the capture compare value for OC2. */
timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);
/* -- OC3 and OC3N configuration -- */
/* Configure global mode of line 3. */
timer_enable_oc_preload(TIM1, TIM_OC3);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
/* Configure OC3. */
timer_set_oc_polarity_high(TIM1, TIM_OC3);
timer_set_oc_idle_state_unset(TIM1, TIM_OC3);
/* Configure OC3N. */
timer_set_oc_polarity_high(TIM1, TIM_OC3N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC3N);
/* Set the capture compare value for OC3. */
timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100);
/* Reenable outputs. */
timer_enable_oc_output(TIM1, TIM_OC1);
timer_enable_oc_output(TIM1, TIM_OC1N);
timer_enable_oc_output(TIM1, TIM_OC2);
timer_enable_oc_output(TIM1, TIM_OC2N);
timer_enable_oc_output(TIM1, TIM_OC3);
timer_enable_oc_output(TIM1, TIM_OC3N);
/* ---- */
/* ARR reload enable. */
timer_enable_preload(TIM1);
/*
* Enable preload of complementary channel configurations and
* update on COM event.
*/
//timer_enable_preload_complementry_enable_bits(TIM1);
timer_disable_preload_complementry_enable_bits(TIM1);
/* Enable outputs in the break subsystem. */
timer_enable_break_main_output(TIM1);
/* Generate update event to reload all registers before starting*/
timer_generate_event(TIM1, TIM_EGR_UG);
/* Counter enable. */
timer_enable_counter(TIM1);
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_COMIE);
/*********/
/*Capture compare interrupt*/
//enable capture compare interrupt
timer_enable_update_event(TIM1);
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_CC1IE);
timer_enable_irq(TIM1, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
}
static void tim_setup(void) {
/* Enable TIM1 clock. */
rcc_periph_clock_enable(RCC_TIM1);
/* Configure TIM1_CH1 and TIM1_CH2 as inputs */
gpio_set_mode(GPIO_BANK_TIM1_CH1, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH1);
gpio_set_mode(GPIO_BANK_TIM1_CH2, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH2);
/* Enable TIM1 interrupt. */
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
/* Reset TIM1 peripheral. */
/* timer_reset(TIM1); */
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* set prescaler value -> 1us */
timer_set_prescaler(TIM1, 72 - 1);
timer_set_period(TIM1, 0xFFFF);
timer_set_repetition_counter(TIM1, 0);
/* Enable preload */
/* timer_disable_preload(TIM1); */
/* Continous mode */
timer_continuous_mode(TIM1);
/* configure Channel 1 */
timer_ic_set_input(TIM1, TIM_IC1, TIM_IC_IN_TI1);
timer_ic_set_filter(TIM1, TIM_IC1, TIM_IC_OFF);
timer_ic_set_polarity(TIM1, TIM_IC1, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC1, TIM_IC_PSC_OFF);
timer_ic_enable(TIM1, TIM_IC1);
timer_clear_flag(TIM1, TIM_SR_CC1IF);
timer_enable_irq(TIM1, TIM_DIER_CC1IE);
/* configure Channel 2 */
timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
timer_ic_enable(TIM1, TIM_IC2);
timer_clear_flag(TIM1, TIM_SR_CC2IF);
timer_enable_irq(TIM1, TIM_DIER_CC2IE);
timer_enable_counter(TIM1);
#if 0
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_disable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM1);
/* Counter enable. */
timer_enable_counter(TIM1);
/* Enable commutation interrupt. */
timer_enable_irq(TIM1, TIM_DIER_CC1IE);
#endif
}
void tim1_trg_com_tim11_isr(void)
{
static int step = 0;
/* Clear the COM trigger interrupt flag. */
timer_clear_flag(TIM1, TIM_SR_COMIF);
/*
* A simplified and inefficient implementation of PWM On
* scheme. Look at the implementation in Open-BLDC on
* http://open-bldc.org for the proper implementation. This
* one only serves as an example.
*
* Table of the PWM scheme zone configurations when driving:
* @verbatim
* | 1| 2| 3| 4| 5| 6|
* -+--+--+--+--+--+--+
* A|p+|++| |p-|--| |
* -+--+--+--+--+--+--+
* B| |p-|--| |p+|++|
* -+--+--+--+--+--+--+
* C|--| |p+|++| |p-|
* -+--+--+--+--+--+--+
* | | | | | | '- 360 Deg
* | | | | | '---- 300 Deg
* | | | | '------- 240 Deg
* | | | '---------- 180 Deg
* | | '------------- 120 Deg
* | '---------------- 60 Deg
* '------------------- 0 Deg
*
* Legend:
* p+: PWM on the high side
* p-: PWM on the low side
* --: Low side on
* ++: High side on
* : Floating/NC
* @endverbatim
*/
//gpio_port_write(GPIOD, GPIO13);
//GPIOD_BSRR = GPIO13; /* LED on */
gpio_port_write(GPIOD, GPIO13);
switch (step) {
case 0: /* A PWM HIGH, B OFF, C LOW */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_LOW);
timer_enable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC1N);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC2N);
timer_enable_oc_output(TIM1, TIM_OC3);
timer_enable_oc_output(TIM1, TIM_OC3N);
step++;
//gpio_port_write(GPIOD, GPIO12);
break;
case 1: /* A HIGH, B PWM LOW, C OFF */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN);
timer_enable_oc_output(TIM1, TIM_OC1);
timer_enable_oc_output(TIM1, TIM_OC1N);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_enable_oc_output(TIM1, TIM_OC2N);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC3N);
step++;
//gpio_port_write(GPIOD, GPIO13);
break;
case 2: /* A OFF, B LOW, C PWM HIGH */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_LOW);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC1N);
timer_enable_oc_output(TIM1, TIM_OC2);
timer_enable_oc_output(TIM1, TIM_OC2N);
timer_enable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC3N);
step++;
//gpio_port_write(GPIOD, GPIO14);
break;
case 3: /* A PWM LOW, B OFF, C HIGH */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FROZEN);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output(TIM1, TIM_OC1);
timer_enable_oc_output(TIM1, TIM_OC1N);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC2N);
timer_enable_oc_output(TIM1, TIM_OC3);
timer_enable_oc_output(TIM1, TIM_OC3N);
step++;
//gpio_port_write(GPIOD, GPIO15);
break;
case 4: /* A LOW, B PWM HIGH, C OFF */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FORCE_LOW);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FROZEN);
timer_enable_oc_output(TIM1, TIM_OC1);
timer_enable_oc_output(TIM1, TIM_OC1N);
timer_enable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC2N);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC3N);
step++;
//gpio_port_write(GPIOD, GPIO15);
break;
case 5: /* A OFF, B HIGH, C PWM LOW */
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC1N);
timer_enable_oc_output(TIM1, TIM_OC2);
timer_enable_oc_output(TIM1, TIM_OC2N);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_enable_oc_output(TIM1, TIM_OC3N);
step = 0;
//gpio_port_write(GPIOD, GPIO15);
break;
}
}
/*--------------------------------------------------------------------*/
void hardware_setup(void)
{
/* Setup the clock to 72MHz from the 8MHz external crystal */
rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable GPIOA, GPIOB and GPIOC clocks.
APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR)
Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN
for Alternate Function clock */
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_periph_clock_enable(RCC_AFIO);
/* Digital Test output PC0 */
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
/* ----------------- Timer 2 Interrupt and DAC control*/
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Continous mode. */
timer_continuous_mode(TIM2);
timer_set_period(TIM2, 1000);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ARR reload disable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* Set port PA4 for DAC1 to 'alternate function'. Output driver mode is ignored. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
/* Enable the DAC clock on APB1 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
/* Setup the DAC, software trigger source. Assume the DAC has
woken up by the time the first interrupt occurs */
dac_trigger_enable(CHANNEL_D);
dac_set_trigger_source(DAC_CR_TSEL1_SW | DAC_CR_TSEL2_SW);
dac_enable(CHANNEL_D);
dac_load_data_buffer_dual(0, 0, RIGHT8);
}
void actuators_pwm_arch_init(void) {
/*-----------------------------------
* Configure timer peripheral clocks
*-----------------------------------*/
/* TIM3, TIM4 and TIM5 clock enable */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
#if REMAP_SERVOS_5AND6
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM5EN);
#else
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN);
#endif
#if USE_SERVOS_7AND8
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN);
#endif
/*----------------
* Configure GPIO
*----------------*/
/* GPIO A,B and C clock enable */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_AFIOEN);
/* TIM3 GPIO for PWM1..4 */
AFIO_MAPR |= AFIO_MAPR_TIM3_REMAP_FULL_REMAP;
gpio_set_mode(GPIO_BANK_TIM3_FR,
GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
GPIO_TIM3_FR_CH1 |
GPIO_TIM3_FR_CH2 |
GPIO_TIM3_FR_CH3 |
GPIO_TIM3_FR_CH4);
/* TIM4 GPIO for PWM7..8 */
#if USE_SERVOS_7AND8
gpio_set_mode(GPIO_BANK_TIM4,
GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
GPIO_TIM4_CH1 |
GPIO_TIM4_CH2);
#endif
/* TIM4/5 GPIO for PWM6..7 */
#if REMAP_SERVOS_5AND6
gpio_set_mode(GPIO_BANK_TIM5,
GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
GPIO_TIM5_CH1 |
GPIO_TIM5_CH2);
#else
gpio_set_mode(GPIO_BANK_TIM4,
GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
GPIO_TIM4_CH3 |
GPIO_TIM4_CH4);
#endif
/*---------------
* Timer 3 setup
*---------------*/
timer_reset(TIM3);
/* Timer global mode:
* - No divider.
* - Alignement edge.
* - Direction up.
*/
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM3, (PCLK / ONE_MHZ_CLK) - 1); // 1uS
timer_disable_preload(TIM3);
timer_continuous_mode(TIM3);
timer_set_period(TIM3, (ONE_MHZ_CLK / SERVO_HZ) - 1);
/* Disable outputs. */
timer_disable_oc_output(TIM3, TIM_OC1);
timer_disable_oc_output(TIM3, TIM_OC2);
timer_disable_oc_output(TIM3, TIM_OC3);
timer_disable_oc_output(TIM3, TIM_OC4);
/* -- Channel configuration -- */
actuators_pwm_arch_channel_init(TIM3, TIM_OC1);
actuators_pwm_arch_channel_init(TIM3, TIM_OC2);
actuators_pwm_arch_channel_init(TIM3, TIM_OC3);
actuators_pwm_arch_channel_init(TIM3, TIM_OC4);
/*
* Set initial output compare values.
* Note: Maybe we should preload the compare registers with some sensible
* values before we enable the timer?
*/
//timer_set_oc_value(TIM3, TIM_OC1, 1000);
//timer_set_oc_value(TIM3, TIM_OC2, 1000);
//timer_set_oc_value(TIM3, TIM_OC3, 1000);
//timer_set_oc_value(TIM3, TIM_OC4, 1000);
/* -- Enable timer -- */
/*
* ARR reload enable.
* Note: In our case it does not matter much if we do preload or not. As it
* is unlikely we will want to change the frequency of the timer during
* runtime anyways.
*/
timer_enable_preload(TIM3);
/* Counter enable. */
timer_enable_counter(TIM3);
#if (!REMAP_SERVOS_5AND6 || USE_SERVOS_7AND8)
#if !REMAP_SERVOS_5AND6
#pragma message "Not remapping servos 5 and 6 using PB8 and PB9 -> TIM4"
#endif
#if USE_SERVOS_7AND8
#pragma message "Enabeling sevros 7 and 8 on PB6, PB7 -> TIM4"
#endif
/*---------------
* Timer 4 setup
*---------------*/
timer_reset(TIM4);
/* Timer global mode:
* - No divider.
* - Alignement edge.
* - Direction up.
*/
timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM4, (PCLK / ONE_MHZ_CLK) - 1); // 1uS
timer_disable_preload(TIM4);
timer_continuous_mode(TIM4);
#ifdef SERVO_HZ_SECONDARY
timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1);
#else
timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ) - 1);
#endif
/* Disable outputs. */
#if USE_SERVOS_7AND8
timer_disable_oc_output(TIM4, TIM_OC1);
timer_disable_oc_output(TIM4, TIM_OC2);
#endif
#if !REMAP_SERVOS_5AND6
timer_disable_oc_output(TIM4, TIM_OC3);
timer_disable_oc_output(TIM4, TIM_OC4);
#endif
/* -- Channel configuration -- */
#if USE_SERVOS_7AND8
actuators_pwm_arch_channel_init(TIM4, TIM_OC1);
actuators_pwm_arch_channel_init(TIM4, TIM_OC2);
#endif
#if !REMAP_SERVOS_5AND6
actuators_pwm_arch_channel_init(TIM4, TIM_OC3);
actuators_pwm_arch_channel_init(TIM4, TIM_OC4);
#endif
/*
* Set initial output compare values.
* Note: Maybe we should preload the compare registers with some sensible
* values before we enable the timer?
*/
#if USE_SERVOS_7AND8
//timer_set_oc_value(TIM4, TIM_OC1, 1000);
//timer_set_oc_value(TIM4, TIM_OC2, 1000);
#endif
#if ! REMAP_SERVOS_5AND6
//timer_set_oc_value(TIM4, TIM_OC3, 1000);
//timer_set_oc_value(TIM4, TIM_OC4, 1000);
#endif
/* -- Enable timer -- */
/*
* ARR reload enable.
* Note: In our case it does not matter much if we do preload or not. As it
* is unlikely we will want to change the frequency of the timer during
* runtime anyways.
*/
timer_enable_preload(TIM4);
/* Counter enable. */
timer_enable_counter(TIM4);
#endif
#if REMAP_SERVOS_5AND6
#pragma message "Remapping servo outputs 5 and 6 to PA0,PA1 -> TIM5"
/*---------------
* Timer 5 setup
*---------------*/
timer_reset(TIM5);
/* Timer global mode:
* - No divider.
* - Alignement edge.
* - Direction up.
*/
timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_prescaler(TIM5, (PCLK / ONE_MHZ_CLK) - 1); // 1uS
timer_disable_preload(TIM5);
timer_continuous_mode(TIM5);
#ifdef SERVO_HZ_SECONDARY
timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1);
#else
timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ) - 1);
#endif
/* Disable outputs. */
timer_disable_oc_output(TIM5, TIM_OC1);
timer_disable_oc_output(TIM5, TIM_OC2);
/* -- Channel configuration -- */
actuators_pwm_arch_channel_init(TIM5, TIM_OC1);
actuators_pwm_arch_channel_init(TIM5, TIM_OC2);
/*
* Set the capture compare value for OC1.
* Note: Maybe we should preload the compare registers with some sensible
* values before we enable the timer?
*/
//timer_set_oc_value(TIM5, TIM_OC1, 1000);
//timer_set_oc_value(TIM5, TIM_OC2, 1000);
/* -- Enable timer -- */
/*
* ARR reload enable.
* Note: In our case it does not matter much if we do preload or not. As it
* is unlikely we will want to change the frequency of the timer during
* runtime anyways.
*/
timer_enable_preload(TIM5);
/* Counter enable. */
timer_enable_counter(TIM5);
#endif
}
void voltage_switch_inverter_VSI(int S_A, int S_B, int S_C)
{
/*
float duty_a=1.0f;
float duty_b=1.0f;
float duty_c=1.0f;
float attenuation =1.0f;
*/
close_loop=true;
cur_angle+=2.0f*PI*TICK_PERIOD*ref_freq;
//converting big angles into something between 0 and 2pi
if (cur_angle >= (2.0f*PI)) {
cur_angle=cur_angle-(2.0f*PI);
}
//close_loop=false;
if (!close_loop)
{
duty_a=sinf(cur_angle);
duty_b=sinf(cur_angle+2.0f*PI/3.0f);
duty_c=sinf(cur_angle+4.0f*PI/3.0f);
}
else
{
duty_a=1.0f;
duty_b=1.0f;
duty_c=1.0f;
attenuation =1.0f;//0.5f;//1.0f;
}
if (motor_off)
{
duty_a=0.0f;
duty_b=0.0f;
duty_c=0.0f;
attenuation=1.0f;
}
/*
//#define CURRENT_LIMIT 14.0f
if ( i_sA >CURRENT_LIMIT || i_sA <-CURRENT_LIMIT ||
i_sB >CURRENT_LIMIT || i_sB <-CURRENT_LIMIT ||
(-i_sA-i_sB)>CURRENT_LIMIT || (-i_sA-i_sB)<-CURRENT_LIMIT)
{
duty_a=0.0f;
duty_b=0.0f;
duty_c=0.0f;
attenuation=1.0f;
motor_stop=true;
//printf("\n\nMotor off, overcurrent...\n\n");
}
*/
/* //PWM mode
TIM_OCM_FROZEN,
TIM_OCM_ACTIVE,
TIM_OCM_INACTIVE,
TIM_OCM_TOGGLE,
TIM_OCM_FORCE_LOW,
TIM_OCM_FORCE_HIGH,
TIM_OCM_PWM1,
TIM_OCM_PWM2,
*/
//dtc switching selection
if (close_loop)
{
//----------------SA: S1 and S4---------------------------------
if (S_A==1)
{
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
//timer_set_oc_mode (TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH);
timer_enable_oc_output (TIM1, TIM_OC1 ); //S1 on
timer_disable_oc_output (TIM1, TIM_OC1N); //S4 off
}
else if (S_A==0)
{
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
//timer_set_oc_mode (TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output (TIM1, TIM_OC1); //S1 off
timer_enable_oc_output (TIM1, TIM_OC1N); //S4 on
}
else
{
duty_a=0.0f;
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
//timer_set_oc_mode (TIM1, TIM_OC1, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output (TIM1, TIM_OC1); //S1 off
timer_disable_oc_output (TIM1, TIM_OC1N); //S4 on
}
//-------------SB: S3 and S6------------------------------------
if (S_B==1)
{
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH);
timer_enable_oc_output(TIM1, TIM_OC2 ); //S3 on
timer_disable_oc_output (TIM1, TIM_OC2N); //S6 off
}
else if (S_B==0)
{
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output(TIM1, TIM_OC2 ); //S3 off
timer_enable_oc_output (TIM1, TIM_OC2N); //S6 on
}
else
{
duty_b=0.0f;
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output(TIM1, TIM_OC2 ); //S3 off
timer_disable_oc_output (TIM1, TIM_OC2N); //S6 on
}
//-----------SC: S5 and S2--------------------------------------
if (S_C==1)
{
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH);
timer_enable_oc_output(TIM1, TIM_OC3 ); //S5 on
timer_disable_oc_output (TIM1, TIM_OC3N); //S2 off
}
else if (S_C==0)
{
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output(TIM1, TIM_OC3 ); //S5 off
timer_enable_oc_output (TIM1, TIM_OC3N); //S2 on
}
else
{
duty_c=0.0f;
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
//timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_FORCE_HIGH);
timer_disable_oc_output(TIM1, TIM_OC3 ); //S5 off
timer_disable_oc_output (TIM1, TIM_OC3N); //S2 on
}
}
//open loop switching selection
/*
else
{
if (duty_a < 0.0f)
{
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_disable_oc_output(TIM1,TIM_OC1);
timer_enable_oc_output (TIM1, TIM_OC1N);
duty_a=-duty_a;
}
else
{
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
timer_enable_oc_output(TIM1, TIM_OC1 );
timer_disable_oc_output (TIM1, TIM_OC1N);
}
if (duty_b < 0.0f)
{
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_disable_oc_output(TIM1, TIM_OC2 );
timer_enable_oc_output (TIM1, TIM_OC2N);
duty_b=-duty_b;
}
else
{
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
timer_enable_oc_output(TIM1, TIM_OC2 );
timer_disable_oc_output (TIM1, TIM_OC2N);
}
if (duty_c < 0.0f)
{
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_disable_oc_output(TIM1, TIM_OC3 );
timer_enable_oc_output (TIM1, TIM_OC3N);
duty_c=-duty_c;
}
else
{
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
timer_enable_oc_output(TIM1, TIM_OC3 );
timer_disable_oc_output (TIM1, TIM_OC3N);
}
}
*/
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC1, duty_a*attenuation*PWM_PERIOD_ARR);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC2, duty_b*attenuation*PWM_PERIOD_ARR);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC3, duty_c*attenuation*PWM_PERIOD_ARR);
//tim_force_update_event(TIM1);
}
