static void platform_init_pwm() {
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO7);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8);
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9);
gpio_set_af(GPIOC, GPIO_AF2, GPIO6);
gpio_set_af(GPIOC, GPIO_AF2, GPIO7);
gpio_set_af(GPIOC, GPIO_AF2, GPIO8);
gpio_set_af(GPIOC, GPIO_AF2, GPIO9);
timer_reset(TIM3);
timer_disable_oc_output(TIM3, TIM_OC1);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 72ish Hz, close to 60 */
timer_set_period(TIM3, 65535);
timer_set_prescaler(TIM3, 16);
timer_disable_preload(TIM3);
timer_continuous_mode(TIM3);
/* Setup output compare registers */
timer_ic_set_input(TIM3, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC1, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC1);
timer_enable_oc_output(TIM3, TIM_OC1);
timer_ic_set_input(TIM3, TIM_IC2, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC2);
timer_disable_oc_preload(TIM3, TIM_OC2);
timer_set_oc_slow_mode(TIM3, TIM_OC2);
timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC2, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC2);
timer_enable_oc_output(TIM3, TIM_OC2);
timer_ic_set_input(TIM3, TIM_IC3, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC3);
timer_disable_oc_preload(TIM3, TIM_OC3);
timer_set_oc_slow_mode(TIM3, TIM_OC3);
timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC3, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC3);
timer_enable_oc_output(TIM3, TIM_OC3);
timer_ic_set_input(TIM3, TIM_IC4, TIM_IC_OUT);
timer_disable_oc_clear(TIM3, TIM_OC4);
timer_disable_oc_preload(TIM3, TIM_OC4);
timer_set_oc_slow_mode(TIM3, TIM_OC4);
timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1);
timer_set_oc_value(TIM3, TIM_OC4, 0);
timer_set_oc_polarity_high(TIM3, TIM_OC4);
timer_enable_oc_output(TIM3, TIM_OC4);
timer_enable_counter(TIM3);
}
void enable_test_trigger(trigger_type trig, unsigned int rpm) {
if (trig != FORD_TFI) {
return;
}
timeval_t t = time_from_rpm_diff(rpm, 45);
/* Set up TIM5 as 32bit clock */
rcc_periph_clock_enable(RCC_TIM5);
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0);
gpio_set_af(GPIOA, GPIO_AF2, GPIO0);
timer_reset(TIM5);
timer_disable_oc_output(TIM5, TIM_OC1);
timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM5, (unsigned int)t);
timer_set_prescaler(TIM5, 0);
timer_disable_preload(TIM5);
timer_continuous_mode(TIM5);
/* Setup output compare registers */
timer_ic_set_input(TIM5, TIM_IC1, TIM_IC_OUT);
timer_disable_oc_clear(TIM5, TIM_OC1);
timer_disable_oc_preload(TIM5, TIM_OC1);
timer_set_oc_slow_mode(TIM5, TIM_OC1);
timer_set_oc_mode(TIM5, TIM_OC1, TIM_OCM_TOGGLE);
timer_set_oc_value(TIM5, TIM_OC1, t);
timer_set_oc_polarity_high(TIM5, TIM_OC1);
timer_enable_oc_output(TIM5, TIM_OC1);
timer_enable_counter(TIM5);
}
/**
* Initialize the DSM timer
*/
static void timer_dsm_init(void) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
// Enable the timer NVIC
nvic_enable_irq(TIMER_DSM_NVIC);
nvic_set_priority(TIMER_DSM_NVIC, 1);
// Setup the timer
timer_disable_counter(TIMER_DSM);
timer_reset(TIMER_DSM);
timer_set_mode(TIMER_DSM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_disable_preload(TIMER_DSM);
timer_continuous_mode(TIMER_DSM);
// Disable interrupts on Compare 1
timer_disable_irq(TIMER_DSM, TIM_DIER_CC1IE);
// Clear the Output Compare of OC1
timer_disable_oc_clear(TIMER_DSM, TIM_OC1);
timer_disable_oc_preload(TIMER_DSM, TIM_OC1);
timer_set_oc_slow_mode(TIMER_DSM, TIM_OC1);
timer_set_oc_mode(TIMER_DSM, TIM_OC1, TIM_OCM_FROZEN);
// Set timer updates each 10 microseconds
#if DEBUG && !DSM_RECEIVER && !DSM_MITM
timer_set_prescaler(TIMER_DSM, 720000 - 1);
#else
timer_set_prescaler(TIMER_DSM, 720 - 1);
#endif
timer_set_period(TIMER_DSM, 65535);
// Start the timer
timer_enable_counter(TIMER_DSM);
}
/******************************************************************************
Initializes the timer, turn on the interrupt and put the interrupt time to zero
INPUT void
OUTPUT void
The timer is set to roll over at 0.5 second from an 8us clock, and the output
compare 1 is used to trigger an alarm. This is set progressively by the
CanFestival stack.
******************************************************************************/
void initTimer(void)
{
/* Set alarm back to zero */
timerAlarm = 0;
/* Enable TIM3 clock. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
/* Enable TIM3 interrupt. */
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_reset(TIM3);
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Set prescaler to give 8us clock */
timer_set_prescaler(TIM3, 576);
/* Set the period as 0.5 second */
timer_set_period(TIM3, TIMEVAL_MAX);
/* Disable physical pin outputs. */
timer_disable_oc_output(TIM3, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM3, TIM_OC1);
timer_disable_oc_preload(TIM3, TIM_OC1);
timer_set_oc_slow_mode(TIM3, TIM_OC1);
timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_FROZEN);
/* Set the initial compare value for OC1. */
timer_set_oc_value(TIM3, TIM_OC1, timerAlarm);
/* Continous counting mode. */
timer_continuous_mode(TIM3);
/* ARR reload disable. */
timer_disable_preload(TIM3);
/* Counter enable. */
timer_enable_counter(TIM3);
/* Enable compare match interrupt. */
timer_enable_irq(TIM3, TIM_DIER_CC1IE);
}
static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. */
timer_set_prescaler(TIM2, 36000);
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
static inline void actuators_pwm_arch_channel_init(u32 timer_peripheral,
enum tim_oc_id oc_id) {
timer_disable_oc_clear(timer_peripheral, oc_id);
timer_enable_oc_preload(timer_peripheral, oc_id);
timer_set_oc_slow_mode(timer_peripheral, oc_id);
timer_set_oc_mode(timer_peripheral, oc_id, TIM_OCM_PWM1);
timer_set_oc_polarity_high(timer_peripheral, oc_id);
timer_enable_oc_output(timer_peripheral, oc_id);
}
void PPMin_TIM_Init()
{
/* Enable TIM1 clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
/* No Enable TIM1 interrupt. */
// nvic_enable_irq(NVIC_TIM1_IRQ);
// nvic_set_priority(NVIC_TIM1_IRQ, 16); //High priority
/* Reset TIM1 peripheral. */
timer_disable_counter(TIM1);
timer_reset(TIM1);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value. timer updates each uSecond */
timer_set_prescaler(TIM1, PPMIn_prescaler); // uSecond (72MHz / (35+1) = 2MHz = 0.5uSecond
timer_set_period(TIM1, PPMIn_period); // 3300uSecond= 2MHz*6600times, TIM1_prescaler=0.5uSecond
/* Disable preload. */
timer_disable_preload(TIM1);
/* Continous mode. */
timer_continuous_mode(TIM1);
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
/* Enable CCP1 */
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_disable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
/* Enable commutation interrupt. */
// timer_enable_irq(TIM1, TIM_DIER_CC1IE);
/* Disable CCP1 interrupt. */
timer_disable_irq(TIM1, TIM_DIER_CC1IE);
/* Counter enable. */
timer_disable_counter(TIM1);
}
/** Set PWM channel configuration
*/
void actuators_pwm_arch_channel_init(uint32_t timer_peripheral,
enum tim_oc_id oc_id) {
timer_disable_oc_output(timer_peripheral, oc_id);
//There is no such register in TIM9 and 12.
if (timer_peripheral != TIM9 && timer_peripheral != TIM12)
timer_disable_oc_clear(timer_peripheral, oc_id);
timer_enable_oc_preload(timer_peripheral, oc_id);
timer_set_oc_slow_mode(timer_peripheral, oc_id);
timer_set_oc_mode(timer_peripheral, oc_id, TIM_OCM_PWM1);
timer_set_oc_polarity_high(timer_peripheral, oc_id);
timer_enable_oc_output(timer_peripheral, oc_id);
// Used for TIM1 and TIM8, the function does nothing if other timer is specified.
timer_enable_break_main_output(timer_peripheral);
}
static void platform_init_eventtimer() {
/* Set up TIM2 as 32bit clock */
timer_reset(TIM2);
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(TIM2, 0xFFFFFFFF);
timer_set_prescaler(TIM2, 0);
timer_disable_preload(TIM2);
timer_continuous_mode(TIM2);
/* Setup output compare registers */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Setup input captures for CH2-4 Triggers */
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3);
gpio_set_af(GPIOB, GPIO_AF1, GPIO3);
timer_ic_set_input(TIM2, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_filter(TIM2, TIM_IC2, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC2, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC2);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10);
gpio_set_af(GPIOB, GPIO_AF1, GPIO10);
timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI3);
timer_ic_set_filter(TIM2, TIM_IC3, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC3, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC3);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11);
gpio_set_af(GPIOB, GPIO_AF1, GPIO11);
timer_ic_set_input(TIM2, TIM_IC4, TIM_IC_IN_TI4);
timer_ic_set_filter(TIM2, TIM_IC4, TIM_IC_CK_INT_N_2);
timer_ic_set_polarity(TIM2, TIM_IC4, TIM_IC_FALLING);
timer_ic_enable(TIM2, TIM_IC4);
timer_enable_counter(TIM2);
timer_enable_irq(TIM2, TIM_DIER_CC2IE);
timer_enable_irq(TIM2, TIM_DIER_CC3IE);
timer_enable_irq(TIM2, TIM_DIER_CC4IE);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_set_priority(NVIC_TIM2_IRQ, 0);
}
/*--------------------------------------------------------------------*/
void timer_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
timer_reset(TIM2);
/* Timer global mode: - No divider, Alignment edge, Direction up */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM2);
timer_set_period(TIM2, 1000);
timer_disable_oc_output(TIM2, TIM_OC2 | TIM_OC3 | TIM_OC4);
timer_enable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_TOGGLE);
timer_set_oc_value(TIM2, TIM_OC1, 500);
timer_disable_preload(TIM2);
/* Set the timer trigger output (for the DAC) to the channel 1 output compare */
timer_set_master_mode(TIM2, TIM_CR2_MMS_COMPARE_OC1REF);
timer_enable_counter(TIM2);
}
/**
* Commutation timer hardware initialization.
*/
void comm_tim_init(void)
{
comm_tim_data.freq = 65535;
(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));
/* TIM2 clock enable */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
/* Enable the TIM2 gloabal interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* TIM2 time base configuration */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE,
TIM_CR1_DIR_UP);
/* Set prescaler value */
timer_set_prescaler(TIM2, 4);
/* Disable preload. */
timer_disable_preload(TIM2);
/* Set continous mode. */
timer_continuous_mode(TIM2);
/* Set period to maximum */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* TIM2 Output Compare Timing Mode configuration: Channel1 */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
//timer_set_oc_polarity_high(TIM2, TIM_OC1);
/* Set initial capture compare value for OC1 */
timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq);
/* ARR reload enable */
timer_disable_preload(TIM2);
/* Counter enable */
timer_enable_counter(TIM2);
/* TIM2 Capture Compare 1 IT enable */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* TIM2 Update IT enable */
timer_enable_irq(TIM2, TIM_DIER_UIE);
comm_tim_reset();
}
void motor_TIMER_config(void)
{
timer_period = rcc_ppre1_frequency / 5000;
timer_reset(TIM3);
/* set timer mode no divider ; alignment on edge ; direction up */
timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_continuous_mode(TIM3);
/* Period (5kHz). TIM3 clk source is APB1*/
timer_set_period(TIM3, timer_period);
/* Reset prescaler value. */
timer_set_prescaler(TIM3, 0);
motor_front_left = 0;
motor_rear_left = 0;
motor_front_rigth = 0;
motor_rear_rigth = 0;
/************ channels configuration ************/
timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT);
timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT);
//configure OCx line
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_LEFT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_LEFT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_RIGHT, TIM_OCM_PWM1);
timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_RIGHT, TIM_OCM_PWM1);
//configure OCx output
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_LEFT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_RIGHT);
/* Set the capture compare value */
timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_LEFT, motor_front_left);
timer_set_oc_value(TIM3, MOTOR_PWM_REAR_LEFT, motor_rear_left);
timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_RIGHT, motor_front_rigth);
timer_set_oc_value(TIM3, MOTOR_PWM_REAR_RIGHT, motor_rear_rigth);
timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT);
timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT);
timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT);
timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT);
timer_enable_counter(TIM3);
}
static void tim_setup(void)
{
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Reset prescaler value.
* Running the clock at 5kHz.
*/
/*
* On STM32F4 the timers are not running directly from pure APB1 or
* APB2 clock busses. The APB1 and APB2 clocks used for timers might
* be the double of the APB1 and APB2 clocks. This depends on the
* setting in DCKCFGR register. By default the behaviour is the
* following: If the Prescaler APBx is greater than 1 the derived timer
* APBx clocks will be double of the original APBx frequencies. Only if
* the APBx prescaler is set to 1 the derived timer APBx will equal the
* original APBx frequencies.
*
* In our case here the APB1 is devided by 4 system frequency and APB2
* divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will
* be 2 x APB2. So when we try to calculate the prescaler value we have
* to use rcc_apb1_freqency * 2!!!
*
* For additional information see reference manual for the stm32f4
* familiy of chips. Page 204 and 213
*/
timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000));
/* Enable preload. */
timer_disable_preload(TIM2);
/* Continous mode. */
timer_continuous_mode(TIM2);
/* Period (36kHz). */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
}
static void tim_setup(void) {
/* Enable TIM1 clock. */
rcc_periph_clock_enable(RCC_TIM1);
/* Configure TIM1_CH1 and TIM1_CH2 as inputs */
gpio_set_mode(GPIO_BANK_TIM1_CH1, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH1);
gpio_set_mode(GPIO_BANK_TIM1_CH2, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH2);
/* Enable TIM1 interrupt. */
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
/* Reset TIM1 peripheral. */
/* timer_reset(TIM1); */
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* set prescaler value -> 1us */
timer_set_prescaler(TIM1, 72 - 1);
timer_set_period(TIM1, 0xFFFF);
timer_set_repetition_counter(TIM1, 0);
/* Enable preload */
/* timer_disable_preload(TIM1); */
/* Continous mode */
timer_continuous_mode(TIM1);
/* configure Channel 1 */
timer_ic_set_input(TIM1, TIM_IC1, TIM_IC_IN_TI1);
timer_ic_set_filter(TIM1, TIM_IC1, TIM_IC_OFF);
timer_ic_set_polarity(TIM1, TIM_IC1, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC1, TIM_IC_PSC_OFF);
timer_ic_enable(TIM1, TIM_IC1);
timer_clear_flag(TIM1, TIM_SR_CC1IF);
timer_enable_irq(TIM1, TIM_DIER_CC1IE);
/* configure Channel 2 */
timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2);
timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF);
timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING);
timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF);
timer_ic_enable(TIM1, TIM_IC2);
timer_clear_flag(TIM1, TIM_SR_CC2IF);
timer_enable_irq(TIM1, TIM_DIER_CC2IE);
timer_enable_counter(TIM1);
#if 0
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC4);
/* -- OC1 configuration -- */
/* Configure global mode of line 1. */
timer_disable_oc_clear(TIM1, TIM_OC1);
timer_disable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_slow_mode(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC1, 1000);
/* ---- */
/* ARR reload enable. */
timer_disable_preload(TIM1);
/* Counter enable. */
timer_enable_counter(TIM1);
/* Enable commutation interrupt. */
timer_enable_irq(TIM1, TIM_DIER_CC1IE);
#endif
}
/*--------------------------------------------------------------------*/
void hardware_setup(void)
{
/* Setup the clock to 72MHz from the 8MHz external crystal */
rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable GPIOA, GPIOB and GPIOC clocks.
APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR)
Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN
for Alternate Function clock */
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_periph_clock_enable(RCC_AFIO);
/* Digital Test output PC0 */
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
/* ----------------- Timer 2 Interrupt and DAC control*/
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Continous mode. */
timer_continuous_mode(TIM2);
timer_set_period(TIM2, 1000);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ARR reload disable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* Set port PA4 for DAC1 to 'alternate function'. Output driver mode is ignored. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
/* Enable the DAC clock on APB1 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
/* Setup the DAC, software trigger source. Assume the DAC has
woken up by the time the first interrupt occurs */
dac_trigger_enable(CHANNEL_D);
dac_set_trigger_source(DAC_CR_TSEL1_SW | DAC_CR_TSEL2_SW);
dac_enable(CHANNEL_D);
dac_load_data_buffer_dual(0, 0, RIGHT8);
}