void test_adc (void)
{
uint8_t i = 0;
while (1)
{
/* ADC software trigger per 100ms */
if (_test_mode.trigger_mode == TRIGGER_MODE_SOFTWARE) {
if (timer_timeout_reached(&timeout) && !_data.done) {
adc_start_conversion();
timer_start_timeout(&timeout, 250);
}
}
if (_test_mode.trigger_mode == TRIGGER_MODE_ADTRG) {
if (pio_get_output_data_status(&pin_adtrg[0]))
pio_clear(&pin_adtrg[0]);
else
pio_set(&pin_adtrg[0]);
}
/* Check if ADC sample is done */
if (_data.done & ADC_DONE_MASK) {
for (i = 0; i < NUM_CHANNELS; ++i) {
printf(" CH%02d: %04d ", _data.channel[i],
(_data.value[i]* VREF/MAX_DIGITAL) );
}
printf("\r");
_data.done = 0;
}
}
}
int16_t get_adc_conv (uint8_t channel)
{
int16_t x = 0x0000 ;
switch (channel) {
case ADC_CHANNEL_0:
case ADC_CHANNEL_1:
case ADC_CHANNEL_4:
case ADC_CHANNEL_5:
if (_data.done & ADC_DONE_MASK) {
x = _data.value[channel];
}
break;
default:
if (timer_timeout_reached(&timeout)) {
_data.done = 0;
adc_start_conversion();
timer_start_timeout(&timeout, 250);
}
break;
}
return x;
}
bool qspi_perform_command(Qspi *qspi, const struct _qspi_cmd *cmd)
{
uint32_t iar, icr, ifr;
uint32_t offset;
uint8_t *ptr;
iar = 0;
icr = 0;
ifr = (cmd->ifr_width & QSPI_IFR_WIDTH_Msk) | (cmd->ifr_type & QSPI_IFR_TFRTYP_Msk);
/* Compute address parameters */
switch (cmd->enable.address) {
case 4:
ifr |= QSPI_IFR_ADDRL_32_BIT;
/* fallback to the 24-bit address case */
case 3:
iar = (cmd->enable.data) ? 0 : QSPI_IAR_ADDR(cmd->address);
ifr |= QSPI_IFR_ADDREN;
offset = cmd->address;
break;
case 0:
offset = 0;
break;
default:
return false;
}
/* Compute instruction parameters */
if (cmd->enable.instruction) {
icr |= QSPI_ICR_INST(cmd->instruction);
ifr |= QSPI_IFR_INSTEN;
}
/* Compute option parameters */
if (cmd->enable.mode && cmd->num_mode_cycles) {
uint32_t mode_cycle_bits, mode_bits;
icr |= QSPI_ICR_OPT(cmd->mode);
ifr |= QSPI_IFR_OPTEN;
switch (ifr & QSPI_IFR_WIDTH_Msk) {
case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
case QSPI_IFR_WIDTH_DUAL_OUTPUT:
case QSPI_IFR_WIDTH_QUAD_OUTPUT:
mode_cycle_bits = 1;
break;
case QSPI_IFR_WIDTH_DUAL_IO:
case QSPI_IFR_WIDTH_DUAL_CMD:
mode_cycle_bits = 2;
break;
case QSPI_IFR_WIDTH_QUAD_IO:
case QSPI_IFR_WIDTH_QUAD_CMD:
mode_cycle_bits = 4;
break;
default:
return false;
}
mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
switch (mode_bits) {
case 1:
ifr |= QSPI_IFR_OPTL_OPTION_1BIT;
break;
case 2:
ifr |= QSPI_IFR_OPTL_OPTION_2BIT;
break;
case 4:
ifr |= QSPI_IFR_OPTL_OPTION_4BIT;
break;
case 8:
ifr |= QSPI_IFR_OPTL_OPTION_8BIT;
break;
default:
return false;
}
}
/* Set number of dummy cycles */
if (cmd->enable.dummy)
ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
else
ifr |= QSPI_IFR_NBDUM(0);
/* Set data enable */
if (cmd->enable.data) {
ifr |= QSPI_IFR_DATAEN;
/* Special case for Continous Read Mode */
if (!cmd->tx_buffer && !cmd->rx_buffer)
ifr |= QSPI_IFR_CRM_ENABLED;
}
/* Set QSPI Instruction Frame registers */
qspi->QSPI_IAR = iar;
qspi->QSPI_ICR = icr;
qspi->QSPI_IFR = ifr;
/* Skip to the final steps if there is no data */
if (!cmd->enable.data)
goto no_data;
/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
(void)qspi->QSPI_IFR;
/* Send/Receive data */
if (cmd->tx_buffer) {
/* Write data */
#ifdef CONFIG_HAVE_AESB
if(cmd->use_aesb)
ptr = (uint8_t*)get_qspi_aesb_mem_from_addr(qspi);
else
#endif
ptr = (uint8_t*)get_qspi_mem_from_addr(qspi);
qspi_memcpy(ptr + offset, cmd->tx_buffer, cmd->buffer_len);
} else if (cmd->rx_buffer) {
/* Read data */
#ifdef CONFIG_HAVE_AESB
if (cmd->use_aesb)
ptr = (uint8_t*)get_qspi_aesb_mem_from_addr(qspi);
else
#endif
ptr = (uint8_t*)get_qspi_mem_from_addr(qspi);
qspi_memcpy(cmd->rx_buffer, ptr + offset, cmd->buffer_len);
} else {
/* Stop here for continuous read */
return true;
}
no_data:
/* Release the chip-select */
qspi->QSPI_CR = QSPI_CR_LASTXFER;
/* Wait for INSTRuction End */
struct _timeout timeout;
timer_start_timeout(&timeout, cmd->timeout);
while (!(qspi->QSPI_SR & QSPI_SR_INSTRE)) {
if (timer_timeout_reached(&timeout)) {
trace_debug("qspi_perform_command timeout reached\r\n");
return false;
}
}
return true;
}
